UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 1 problems

- D1.10 -

 A: 4-bit radix-2 to Johnson converter

 

B

 

Products

D1.9

D1.11

1.- Specifications of the 4-bit binary radix-2 to Johnson converter

Design the 4-bit binary radix-2 to Johnson code converter represented in Fig. 1.

Binary to Johnson code converter

Fig.1. Symbol of the 4-bit binary to Johnson converter.

Complete its truth table and answer questions such: How many maxterms contain J(6)? How many minterms contain J(1)?

Draw an example of timing diagram to be used later as stimulus in the VHDL testbench when verifying the synthesised circuit. Consider Min_Pulse = 2.78 ms.

The same project B3.10 is proposed in Chapter 3 for learning the basics of μC software organisation and basic digital I/O.

 

CPLD or FPGA target chip options:

 Target option #1.: MAX II

 Target option #2.: MAX 10

 Target option #3.: Cyclone IV

 

2. Planning

Plan A structural circuit based on logic gates and equations in a single VHDL file. We have many strategies, for instance:

option #1: use Minilog to obtain PoS.

Project location:

 C:\CSD\P2\Bin_Johnson_4bit_PoS\(files)

option #2: use Minilog to obtain SoP.

Project location:

 C:\CSD\P2\Bin_Johnson_4bit_SoP\(files)

 

How many FPGA resources (logic cells, logic elements, etc.) are used? What is the percentage of the target chip used in this design?

 

Plan B behavioural approach writing the truth table or the high-level description or algorithm in VHDL in a single file (flat).

Project location:

 C:\CSD\P2\Bin_Johnson_4bit_B\(files)

 

How many FPGA resources (logic cells, logic elements, etc.) are used? What is the percentage of the target chip used in this design?

 

After having studied P4 tutorials, additional questions can be added to our report. For instance: 

 

3. Development

Circuit synthesis. Ideal RTL and technology views. CPLD or FPGA target chip options:

(*) MAX10 chips are not used for running gate-level ModelSim simulation because Intel Quartus Prime does not generate the "*.sdo" file accompanying the "*.vho" translation of the technology view. Thus, you can run the timing analyser as usual, and change to another device family for performing examples of gate-level timing diagrams.

How many FPGA resources (logic cells, logic elements, etc.) are used? What is the percentage of the target chip used in this design?

 

4. Test

 

Chapter 1 problems

- D1.10 -

 B: 4-bit Johnson to radix-2

  

A

 

Products

D1.9

D1.11

1.- Specifications of the 8-bit Johnson to binary radix-2 converter

Design the 8-bit Johnson to binary radix-2 code converter represented in Fig. 1.

Johnson to binary converter

Fig.1. Symbol of the Johnson_bin_8bit converter.

Complete the circuit's truth table and answer questions such: How many maxterms contain B(3)? How many minterms contain B(1)? IS it practical to design the circuit using its canonical equations? Where to find information on how to deal with incomplete functions? Can you add to the symbol and the truth table in Fig. 1 a new output such Error to be set high ('1') when the input presents an illegal Johnson code (as it was the case in the Tank_level_meter example)?

Draw an example of timing diagram to be used later as stimulus in the VHDL testbench when verifying the synthesised circuit. Consider Min_Pulse = 3.45 ms.

 

2. Planning

Plan A structural circuit based on logic gates and equations in a single VHDL file. We have many strategies, for instance:

option #1: use Minilog to obtain PoS.

Project location:

 C:\CSD\P2\Johnson_bin_8bit_PoS\(files)

 

option #2: use Minilog to obtain SoP.

Project location:

 C:\CSD\P2\Johnson_bin_8bit_SoP\(files)

How many FPGA resources (logic cells, logic elements, etc.) are used? What is the percentage of the target chip used in this design?

 

Plan B behavioural approach writing the truth table or the high-level description or algorithm in VHDL in a single file (flat).

Project location:

 C:\CSD\P2\Johnson_bin_8bit_B\(files)

How many FPGA resources (logic cells, logic elements, etc.) are used? What is the percentage of the target chip used in this design?

 

Plan C2 is a hierarchical architecture based (multiple VHDL file) on components and signals.

For instance: using the method of decoders (MoD). Project location:

 C:\CSD\P2\Johnson_bin_8bit_C2\MoD\(files)

 

Plan C2 is a hierarchical architecture based (multiple VHDL file) on components and signals.

For instance: using the method of memories (ROM). Project location:

 C:\CSD\P2\Johnson_bin_8bit_C2\ROM\(files)

 

3. Development

Circuit synthesis. Ideal RTL and technology views. CPLD or FPGA target chip options:

(*) MAX10 chips are not used for running gate-level ModelSim simulation because Intel Quartus Prime does not generate the "*.sdo" file accompanying the "*.vho" translation of the technology view. Thus, you can run the timing analyser as usual, and change to another device family for performing examples of gate-level timing diagrams.

How many FPGA resources (logic cells, logic elements, etc.) are used? What is the percentage of the target chip used in this design?

 

4. Functional test

Testbench fixture and stimulus vectors.

 

5. Gate-level simulation and timing analysis

After having studied P4 lectures and LAB4 tutorials, the project can continue adding the fifth section on time measurements.