UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

PLA1

Q&A

PLA2_3: Designing arithmetic and logic circuits

PLA4

P1 design, P2, P3, LAB 2, LAB 3

Specifications

D1.13 8-bit radix-2 subtractor with BCD inputs and 7-segment display outputs.

NOTE: We use your discussion and feedback to clarify and better organise project specifications, thus you may expect changes on the assignment pages for the good. Notify us whatever detail that is not clear enough. This is a way to put into practice and reinforce teamwork and cooperation between all the company engineers.

Start studying the top circuit and how it may work. Imagine its internal architecture counting the number of projects involved and the total numbers of VHDL files that will be required, whatever you are inventing them or copying and adapting directly from other CSD products.

Options for designing some of the components in the chips. Study individually each project specifications in detail. Large circuits are all of them plan C2, and its architecture is proposed or can be found or adapted from CSD products.

  Project 3
Subt_1bit		 Project 4
Sign_corrector
 Project 7
DM74184 		 Project 5
DM74185		 Project 8
Hex_7seg_decoder		 Project 9
Quad_MUX_2		 Operands for timing diagrams and test benches
Group 1 A.1 C2.1 A B A C2 1
Group 2 A.2 C2.2 B A B B 2
Group 3 B.1 C2.1 A B A C2 3
Group 4 B.2 C2.2 B A B B 1
Group 5 A.2 C2.1 A B A C2 2
Group 6 C2.1 C2.2 B A B B 3
Group 7 C2.2 C2.1 A B A C2 1

Follow this rubric for writing reports.

NOTE: This PLA2_3 must be solved only after having completed successfully lab sessions LAB2 and LAB3 because you will adapt and apply materials and proceedings from them. This project will be continued in PLA4 adding time measurements.

 

NOTE: This is cooperative group work. You must explain in the planning section of your report and video, who is in charge of each section, who is leading the tasks, who is developing the components or sections, who is measuring or testing, etc. It is fundamental in order to obtain good assessments that you explain very well which is the contribution to the final project of each one of the group members.

 

This group submission at Atenea includes the report in a PDF file, the zipped project, a 10 min. max video presentation and also your self-assessment.

 

Notes on how to organise and handwrite PLA2_3 report sections:

 1. Specifications and theory

NOTE: You better add theory, class-notes or other learning materials in section 1 on specifications in one of your projects. Explain, discuss and try to locate in CSD lessons or laboratory tutorials the concepts and tools used in these PLA plans and developments, so that you are sure that these materials will help you to study and solve similar problems for Exam 1.

 

2. Planning

NOTE: One project at a time, starting from the simplest. Solving the next project after having corrected errors from the previous one. Do not worry much if you cannot complete the full PLA2_3 or by the due date it still does not work satisfactory.  This PLA2_3 will be continued in PLA4, where you will be able to include corrections or improvements after our feedback.

Slide

3. Development

4.Test and verification

5. Annexes

Notes on video presentations: 10 min. max., 3 - 4 min. each participant.

The idea of the video presentation is different from the written report and has its own particular objective: develop your oral communications skills in our engineering context in a way a large audience can grasp the main details of your project. Put in motion your communication skills that you will continue to practise and improve through PLA6_7 and PLA10_11. We will focus assessment in how you are organising the presentation, how confident you are in front of the camera, time sharing among students, support materials and audio and video quality. This is an example of final PLA11 presentation. A good idea is to submit a meet recording or equivalent.

===> Do not browse your report pages when presenting, prepare some slides instead.