UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

 

Radix-2 synchronous counter modulo 12 using plan C2

P7

Lab 7

Designing standard sequential circuits using components

1. Specifications Planning Developing Test functional Test gate-level Prototype Report

The same for plan Y and plan X designs. Pictures Fig. 1, Fig.2 and Fig. 3 represent symbol, function table, timing diagram and also the state diagram.

The idea if truncation and expansion is explained in this L7.3 lecture.

 

Specifications 2. Planning Developing Test functional Test gate-level Prototype Report

Hierarchical design using multiple VHDL files and components. The idea is truncating a larger counter like Counter_mod16 that is used as a building block. Discuss how this circuit works in Fig. 12. Study it for instance in two separate design steps:

- Step #1: Up counter considering only the CE control signal)

- Step #2: Add the UD_L control signal and discuss what blocks and logic has to be included in the basic design from phase 1 so that it becomes the circuit in Fig. 12.

Counter truncation (plan C2)

Fig. 12. Example of plan C2 circuit: Counter_mod12 implemented using standard Counter_mod16 building block.

This is your project location:

C:\CSD\P7\Counter_mod12C2\(files)

 

Specifications Planning 3. Developing Test functional Test gate-level Prototype Report

These are the top Counter_mod12.vhd , and component Quad_MUX_2.vhd. In this tutorial there is the Counter_mod16.

Choose a MAX II device EPM2210F324C3 and start a Quartus Prime project.

RTL view

Fig. 13. RTL view translation of Fig. 12 schematic.

 

Terchnology_planC2

Fig. 14. Technology view schematic for a MAX II Intel CPLD. This plan C2 architecture is different from plan Y in Fig. 9, thus it will produce different propagation times.

 

Specifications Planning Developing 4. Test functional Test gate-level Prototype Report

Running ModelSim and using the same testbench in Fig. 10 Counter_mod12_tb.vhd generates waveforms as in Fig. 11.

 

Specifications Planning Developing Test functional 5. Test gate-level Prototype Report

Gate-level simulations in ModelSim

Here is interesting to measure propagation times because we are proposing an alternative architecture that may be faster or slower than the one from plan X or plan Y.

gate_level analysis for PLAN C2 circuit

Fig. 15. Timing analyser spreadsheet for measuring tCO.

 

Quartus Prime timing analyser

TCO measurement

Fig. 15. Timing analyser spreadsheet for measuring tCO.

 

Specifications Planning Developing Test functional Test gate-level 6. Prototype Report

Practice with the example proposed in Lab 7. 

 

Specifications Planning Developing Test functional Test gate-level Prototype 7. Report

Follow this rubric for writing reports.