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Bachelor's Degree in Telecommunications Systems and in Network Engineering |
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Chapter 2 problems |
- D2.21 - |
Programmable timer (version A) |
A |
1. Specifications
Conceive a real-time timer to count CLK pulses as represented in Fig. 1. The timing period will be TP = M·TCLK, where the M parameter can be adjusted to any positive number. After detecting the trigger (TG) positive edge, the timer output (T_Out) signal is kept high for a duration of TP. The trigger pulse must be longer than a CLK period, and the circuit must prevent retriggering if the trigger pulse exceeds the timing period.
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Fig. 1. Initial idea of a configurable timer. |
For example, we can generate a Timer_12_5s circuit with a timing period of TP = 12.5 s using a CLK frequency of 12 kHz, and adjusting the internal parameter M = 150000.
Other ideas on basic analogue timer circuits. The LAB11 projects a microcontroller-based timer.
2. Planning
Let us use the dedicated processor architecture described in lecture L8.1: an FSM controlling a versatile parallel-loadable binary counter.
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Fig. 2. The timer conceived as a simple dedicated processor. The datapath circuit is a configurable counter. |
Four states are required to operate this basic timer, as shown in Fig. 3. There is an extra loop that is used in case the trigger pulse is longer than the timing period
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Fig. 3. State diagram. |
The timing diagram can be inspected in Fig. 4. Complete it with the datapath control signals and also include the internal signals current_state and next_state from the FSM.
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Fig. 4. Example timing diagram that later can be reproduced using ModelSim functional simulations. We can load the counter with a number D = M - 1 (one CLK cycle is used for loading the counter Chip2 ). |
Project location:
C:\CSD\P8\Timer_Tp\(files)
Use plan C2 to assemble all the datapath components. For instance, fixing M = 1024, this file is the Chip2 translation "Counter_mod1024.vhd", inferred using plan Y from the adaptation of the versatile Counter_mod16.
To design the FSM adapt the FSM architecture to this problem, naming and connecting all signals and inputs and outputs.
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Fig. 5. FSM state diagram to control the datapath and generate user outputs. |
Draw the state register memory based on D_FF and deduce the number of D_FF required when encoding the machine using the following options:
Option #1: radix-2 (sequential)
Option #2: Gray
Option #3: Johnson
Option #4: one-hot
Draw the CC2 truth table to obtain the circuit's outputs and its equivalent flowchart behavioural interpretation (plan B).
Draw the CC1 truth table to obtain the circuit's state transitions and its equivalent flowchart behavioural interpretation (plan B).
Write the FSM VHDL file.
Start a Quartus Prime synthesis project for one of the following programmable target chips:
Option #1: Cyclone IV EP4CE115F29C7
Option #2: MAX II EPM2210F324C3
Option #3: MAX 10 10M50DAF484C7 (*)
(*) Remember that this chip does not generate sdo delay files, thus use another one when gate-level simulations are required.
Inspect and annotate the RTL and technology views. Check the number of D_FF synthesised in this application.
Generate a VHDL testbench fixture schematic using two CLK signals.
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Fig. 6. Testbench fixture. What inputs, outputs and internal signals are to be monitored? |
Run functional simulations to verify your design. Visualise as well in the wave timing diagram the internal states.
Run gate-level simulations to measure the propagation time CLK to output (tCO). Measure the minimum TCLK period or the maximum frequency of operation of the FSM.
If you like to time a month (Timer_1month), how to organise the circuit (including a CLK_Generator), how many resources and D_FF will be used in a platform DE10-Lite?
Chapter 2 problems |
- D2.21 - |
Programmable timer (version B) |
B |
1. Specifications
Let us design a 12-bit programmable timer to generate up to eight timing periods TP to be used as a component in other projects. The input Set_T selects one of eight 12-bit radix-2 binary numbers for down-counting. A trigger (TG) pulse initiates the timing cycle; its duration must be larger than TCLK, and to avoid retriggering in case of being longer than TP, another state "Wait_for_trigger_down" must be included (as shown in version A). T_out signal is set while timing. The end-of-timing (EoT) flag is asserted high for a single CLK period to indicate completion of the timing operation and readiness for the next cycle. This configuration allows expandability by connecting the end-of-timing signal to the trigger input of another timer.
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Fig. 1. Prog_timer symbol and waveforms |
Dedicated processor design strategy. Design the project in a single step.
The same project designed programming a μC is in D3.21.
2. Planning
We will adapt the general architecture of a dedicated processor to this project, as shown in Fig. 2.
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Fig. 2. Programmable timer dedicated processor composed of FSM and datapath. |
The timing period is always TP = (Ti + 2)·TCLK. However, if required, a subtractor circuit can be connected to eliminate the two CLK pulses overhead.
Project location:
C:\CSD\P8\Prog_timer\(files)
Use plan C2 to assemble all the datapath components. Use plan B to define the Duodecuple_MUX_8 and plan Y for the Counter_mod_4096.
To design the FSM, adapt the FSM architecture to this problem, naming and connecting all signals and inputs and outputs.
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Fig. 3. FSM state diagram to control the datapath and generate user outputs. |
Draw the state register memory based on D_FF and deduce the number of D_FF required when encoding the machine using the following options:
Option #1: radix-2 (sequential)
Option #2: Gray
Option #3: Johnson
Option #4: one-hot
Draw the CC2 truth table to obtain the circuit's outputs and its equivalent flowchart behavioural interpretation (plan B).
Draw the CC1 truth table to obtain the circuit's state transitions and its equivalent flowchart behavioural interpretation (plan B).
Write the FSM VHDL file.
Start a Quartus Prime synthesis project for one of the following programmable target chips:
Option #1: Cyclone IV EP4CE115F29C7
Option #2: MAX II EPM2210F324C3
Option #3: MAX 10 10M50DAF484C7 (*)
(*) Remember that this chip does not generate sdo delay files; thus, use another one when gate-level simulations are required.
Inspect and annotate the RTL and technology views. Check the number of D_FF synthesised in this application.
Generate a VHDL testbench fixture schematic using two CLK signals.
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Fig. 4. Testbench fixture. What inputs, outputs and internal signals are to be monitored? |
Run functional simulations to verify your design. For instance, you can use a 1 MHz CLK signal and prepare several timing periods TP. Visualise as well the FSM internal states in the wave timing diagram.
Run gate-level simulations to measure the propagation time from CLK to output (tCO). Measure the minimum TCLK period for a given FPGA target chip or equivalently, the maximum operating frequency of the FSM.
Infer and discuss how this circuit can be expanded to any arbitrary large n-bit programmable timer.
Chapter 2 problems |
- D2.21 - |
Programmable timer (version C) |
C |
1. Specifications
Redesign the programmable Timer_MMSS proposed as a highlighted project in P8, replacing the TS_UP and TS_DW push-buttons with a 4-row by 3-column matrix keypad. The timing period TP goes from 1 second (00:01) to 59 minutes 59 seconds (59:59). When the start (ST) key "*" is pressed, the system down-counts from the current MM:SS entered. While down-counting, a LED is blinking with a 0.5 s period (T_LED), and the output T_out is set to keep a relay switch ON.
When the countdown reaches 00:00, the timing period has elapsed, and the system sets the TO_LED and generates an intermittent sound alarm (TO_SW): a 1.2 kHz tone for 5 seconds followed by 3 seconds of silence. This alarm sequence is terminated either by initiating a new timing period or by pressing the "#" key (SP).
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| Fig. 1. Initial sketch and symbol for the electronic circuit representing the keypad, 7-segment digits, LED and other devices. |
An idea of the circuit waveforms is represented in Fig. 2.
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| Fig. 2. Example of timing diagram showing some of the main waveforms. |
2. Planning
The circuit must include several modules to properly perform all the required specifications. Timing data must be able to be loaded from a matrix keypad. The same keypad must generate trigger (TG) and stop (SP) pulses. A BCD counter modulo 3600 will be the most important component of the datapath, in charge of down-counting from the initial set time. An FSM will detect control signals and generate outputs. All the CLK signals will be derived from the CLK_Generator. In a second design phase, a programmable timer will generate the sound wave intermittency.
Plastic and membrane keypad types are represented in Fig. 3. Even if our product for experimentation is 16-key, we can simply use it as 12-key.
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| Fig. 3. Several matrix keypads on columns and rows. |
Design phase #1: The basic MM:SS timer including the keypad and T_out, T_LED,
Fig. 4 shows how the first version of the circuit can be engineered. As usual, most of the components came from our library, such the Matrix_enc_16key_reg to detect when a key is pressed, the CLK_Generator to obtain all the synchronised CLK signals, the Dec_Hex_7seg to drive the seven-segment decoders for minutes and seconds. Other components require slight adaptations, such the Counter_MMSS and the LSR_4digit. Therefore, several design steps are introduced to complete this first design phase.
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| Fig. 4. The main components for the Timer_MMSS. |
Step #1: The keypad interface and the 4-digit left-shift register.
To interface the 12-key matrix keypad we can adapt and include the project highlighted in P6 as Matrix_enc_16key_reg. The wire Column(0) will be left unconnected reading '1'. "F" is the "*" key to trigger the timing period, and "E" is the "#" to stop the alarm.
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| Fig. 5. Connecting the 12-key matrix keypad. |
The digits are left-shifted when clicking numerical keys, and the last four entered digits represent the timing period in minutes and seconds. For instance, to enter a timing period of TP = "53:12", the 7-segment display will show the following sequence: "00:00", "00:05", "00:53", "05:31", "53:12". We can use the basic Data_reg_4bit component to implement this 4-digit left shifter.
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| Fig. 6. Connecting the 12-key matrix keypad. |
Minutes or seconds larger than 59 are invalid and will not allow triggering the timer; an overflow will reset the displays using the additional synchronous reset (RST) control input.
When clicking special keys "*" and "#", the interface generates the control signals trigger (TG) and stop (SP) for commanding the timer.
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| Fig. 7. Auxiliary circuits to detect time set overflow and the special keys hash and asterisk. |
Step #2: Modulo 3600 4-digit BCD down-counter (MM:SS)
A 4-digit modulo 3600 down-counter for minutes and seconds with parallel inputs is required to generate the timing period. A CLK_1Hz signal is required to down-count in real-time. We can enhance the basic Counter_MMSS adding the parallel load (LD) capability as shown in the new symbol and function table in Fig. 8.
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| Fig. 8. a) The Counter_MMSS with parallel inputs and its function table. b) Its internal design as a count expansion enhanced with parallel load to be able to count from any preset value. |
The main component Counter_BCD_mod60 includes now the new control input LD, as shown in Fig. 9.
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| Fig. 9. Symbol and function table for the enhanced Counter_BCD_mod60 with parallel inputs. |
Therefore, as represented in the Fig. 10 schematic, the parallel inputs switched by two new Quad_MUX_2 allows presetting any initial number.
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| Fig. 10. Modifications to the basic Counter_BCD_mod60 schematic to introduce parallel inputs. |
Step #3: The FSM
The main objective is to generate a programmable timer up to one hour, and the FSM will be in charge of sequencing the required operations. We may consider that at any time the user can click the start button (* key) to generate the timing period TP at T_out and the LED intermittency at T_LED. At this design phase, the system goes back to idle once the TP has elapsed.
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| Fig. 11. FSM state diagram. |
Step #4: The CLK_Generator
Design the Chip7 in Fig. 4 adapting the structure studied in L8.2.
Design phase #2: Alarm sound waveforms
Considering the specifications, two timing periods are required once the timing period has elapsed: 5 seconds for the 1.2 kHz alarm tone and 3 seconds for the silence. We can use and adapt the Prog_Timer from B. The FSM in Fig. 11 wil require new states.
Optional Design phase #3: How to enhance the circuit to generate accurate pulses in nanoseconds (ns), microseconds (μs) and milliseconds (ms). The concepts of accuracy, precision, resolution and sensitivity in instrumentation.
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