UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

 

BCD counter modulo 3600 (4-digit, minutes and seconds counter)

P7

1. Specifications

Design the Counter_MMSS the symbol of which is drawn in Fig. 1. It is a 4-digit BCD counter module 3600 divided in two chained SS (modulo 60) and MM (modulo 60) synchronous counters.

Counter_MMSS symbol

Fig 1. Symbol.

 

2. Planning

As represented in Fig. 2, Counter_MMSS can be invented using plan C2 expanding Counter_BCD_mod60 devices.

Counter_MMSS

Fig 2. Inventing the Counter_MMSS (visio) requires chaining Counter_BCD_mod60 blocks for counting seconds and minutes.

Project location:

C:\CSD\P8\Counter_MMSS\(files)  

 

3. Development

Example file translation of schematics above in Fig. 2: Counter_MMSS.vhd, Counter_BCD_mod60.vhd, Quad_MUX_2.vhd, and copy the Counter_mod16.vhd from its plan Y tutorial Counter_mod16.

Fig. 4 and Fig. 5 show RTL and technologies views for a target chip MAX10 10M50DAF484C7.

RTL circuit for the Counter_MMSS

Counter_BCD_mod60

Fig 4. Top Counter_MMSS RTL circuit and its component Counter_BCD_mod60. built chaining basic Counter_mod16.

Total number of registers D_FF is 16. Total logic elements is 79.

Flattened techology view

Fig. 5. Technology view emphasising how the CLK signal is distributed to all 16 D_FF. (pdf)

 

4. Testing (functional)

We need to drive CLK, CD, CE and UD_L in the usual way.

Generate from Quartus Prime the VHDL testbench fixture skeleton. Rename it and move it to the project folder.

Copy from this example file Counter_MMSS_tb.vhd only the stimulus activity described in the two processes and also the constant CLK_Period. 

Start and run a functional simulation project using ModelSim to verify that the device operates correctly. Let us try one mode of operation at a time. For instance, Fig. 6 shows how the circuit is counting down. It need a time of 3600·CLK_Period to complete all counting range.

Functional simulation of the Counter_MMSS

Fig. 6. Simulation results.