UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 1 problems

     - D1.13 -

8-bit subtraction using true subtractors

Products

D1.12

D1.14

1. Specifications

We want to implement a circuit for subtracting 8-bit binary radix-2 numbers as represented in Fig. 1. Including additional circuits we can input operands directly in BCD and represent results in 7-segment displays, which are quite convenient features. In this way we can use the project for learning many Chapter 1 concepts on logic and arithmetic blocks.

Subtractor symbol

Fig. 1. The entity of a Subtractor_8bit and an example operation.

In chapter 2 we can easily introduce a keyboard and data registers to save operands data before calculating results, as in typical calculators. The same project B3.13 is proposed in Chapter 3 for learning the basics of μC software organisation and basic digital I/O.

In this project, for academic purposes, as a variation to the typical arithmetic circuits proposed in P4 for working with integers, we will implement substation operations using true subtractors and introducing a correction mechanism for representing negative numbers. 

The strategy to design the key component Subt_8bit is to use plan C2 chaining up to eight 1-bit subtractors Subt_1bit instead of the standard way based on 1-bit adders and two's complement convention discussed in P4. Fig. 2 shows the truth table of the Subt_1bit component.

Subt_1bit circuit

Fig. 2. The idea of the basic Subt_1bit and its truth table. This basic circuit has three inputs (minuend, subtrahend and borrow) and two outputs (difference and borrow), similarly to the basic Adder_1bit.

Fig. 3 shows how to chain Subt_1bit using plan C2 to generate true subtractors of any size, for example, the Subt_8bit (Chip1) required in this project. It looks quite similar to what was proposed for chaining standard adders. 

Hence, for building a Subt_nbit we chain up to n Subt_1bit components by rippling borrow signals in the same way we connect carries when building our ripple-carry adders in LAB3.

8-bit circuit

Fig. 3. The internal architecture for our Subt_8bit chaining Subt_1bit components. 

Draw the testbench fixture and an example of timing diagram to be used later as stimulus in the VHDL verification of the synthesised circuit. You can use as example test vectors for operands A (minuend) and B (subtrahend). Add other numbers if you liked it.

Picture report

Fig. 4. Timing diagram example for the Subtactor_8bit considering for the test vectors.

This device will work correctly only for natural numbers where A > B. Thus, deduce which kind of algorithm and circuits may be used to display correct values even for negative results.

Operation example

Operation with negative results

Fig. 5. Example operation when using the Subt_8bit for A < B. Perform other similar operations to visualise the algorithm required for correcting negative results and being able to display them correctly.

 

2. Planning

The hierarchical architecture proposed for solving this project is represented in Fig. 6. To obtain a variety of solutions we also include options for the components to allow us covering much of the Chapter 1 content.

Planning schematic

Fig. 5. Proposed fully-annotated architecture for the full Subtractor_8bit ready for VHDL translation.

Subt_1bit. We can practice using several CSD design strategies presented in L1.4.

Option #A.1: plan A. Equations using only NAND2 gates.

Option #A.2: plan A. Equations using Subt_1bit using PoS.

Option #B.1: plan B. Truth table captured using a schematic.

Option #B.2: plan B. Truth table captured using a flowchart.

Option #C2.1: plan C2. Using the MoD

Option #C2.2: plan C2. Using the MoM and MUX_2

 

Chip2, Sign_corrector. When the result from Chip1 generates Bout = '1' = N the numbers to represent on the displays will be negative. We need to represent the result's absolute value accompanied by the sign LED. This is the task for the Chip2. 

The Chip2 can be designed internally using two options as shown in these examples. The idea is to calculate the two's complement when N = '1' and do nothing when N = '0' (buffer). The two's complement can be obtained using both Adder_8bit as presented in P4 and also using another Subt_8bit.

Sign corrrection

Sign correction example

Fig. 6. Example operations to generate the absolute value with the Sign_corrector.

Option #C2.1: plan C2. Using an Adder_8bit

Option #C2.2: plan C2. Using the Subt_8bit

Options to generate the Sign_corrector circuit

Fig. 7. Two schematics for implementing the Sign_corrector.

 

Chip5, code converter Bin_BCD_8bit solved applying plan C2 from our similar products. We propose two alternatives for the basic component DM74185 included in the circuit:

Option #A: plan A. Equations from Minilog

Option #B: plan B. Truth table or algorithm captured using a schematic or flowchart

 

Chip3, Chip4, code converter BCD_bin_3digit solved applying plan C2 from our similar products. We propose two options for the basic component DM74184 proposed in D1.15:

Option #A: plan A. Equations from Minilog

Option #B: plan B. Truth table or algorithm captured using a schematic or flowchart

As shown in Fig. 5, these chips also generate EA and EB, error signals to be high when any BCD input is larger than '9'. And using gates and the most significant bits of M and S, we can also detect using EC when input numbers are larger than 255, the range of Chip1 to perform subtractions.

Chip6, Chip7, Chip8, decoders hexadecimal to 7-segments Dec_Hex_7seg using two options for its internal component Hex_7seg_decoder:

Option #A: plan A. Equations from Minilog

Option #B: plan B. Truth table or algorithm captured using a schematic or flowchart

 

Chip9, quadruple 4-channel multiplexer using two options:

Option #B: plan B. Truth table or algorithm captured using a schematic or flowchart.

Option #C2: plan C2. Using MUX_2 components and other logic if necessary (circuit expansion)

 

 

3. Planning

Develop the circuit targeting the board DE10_Lite chip MAX 10.

 

4. Testing (functional)

Test your circuit writing a VHDL simulation testbench from the timing diagram in the specifications.

 

5. Testing (gate-level)

Indications for PLA4. Test your circuit and measure both, propagation delays in a given transition and the Subtractor_8bit maximum speed of computation.

 

Annexes

Explain the design of components that you invent and that are not found in our libraries.

 

 

Lab groups

One way to assign this project in lab groups is using this table:

Example of group options
  Subt_1bit Chip2 Chip3, Chip4 Chip5 Chip6,Chip7, Chip8 Chip9 Test vectors options
Group 1 A.1 C2.1 A B A C2 1
Group 2 A.2 C2.2 B A B B 2
Group 3 B.1 C2.1 A B A C2 3
Group 4 B.2 C2.2 B A B B 1
Group 5 A.2 C2.1 A B A C2 2
Group 6 C2.1 C2.2 B A B B 3
Group 7 C2.2 C2.1 A B A C2 1