CSD reports for work in progress or submissions are corrected and assessed accordingly to these general ideas:

• Start writing your report only when your project works correctly.

• VHDL reports in Chapters 1 and 2 have at least four sheets of paper, each one representing a project section: (1) specifications - (2) planning - (3) development - (4) verification.

• C language reports in Chapter 3 have at least three sheets of paper, each one representing a project section: (1) specifications - (2) planning - (3 - 4) interactive development and testing (debugging).

• Circuit analysis. Every analysis method in P1 section A and in P5 is a report. For instance, analysing a logic circuit using Proteus requires (1) specifications - (2) planning what you are going to do when using Proteus - (3) development: capturing the circuit using the given library of components and running the simulation to obtain the circuit's truth table - (4) verification: a text paragraph explaining that you have got the same result (truth table) running at least another method, for instance method III.

• Circuit design. Every design project (plan A, B, C1, C2, X, Y) is a report. For instance inventing a combinational circuit using plan A requires the four sections: (1) specifications: truth table, symbol, etc. - (2) planning: what plan A equation strategy are you using - (3) development: design steps using EDA tools to synthesise your circuit - (4) verification: using VHDL simulation to check that the circuit generates the specified truth table. 

• Theory and other learning materials are attached to section (1). If you are given several project assignments, include theory only in one project report.

• When using plan C2, report sections are referring to the main (top) project in design. Other designed components or collateral tutorial work or related theory can be added to the report as annexes. 

• Sketches, schematics, diagrams are handwritten and original. Draw and adapt our materials from digsys or from books.  

• Word processors are not used in CSD, use handwritten text instead. For this introductory course on digital design word processors are simply a waste of study time.

• Academic integrity at the UPC is always considered. Two o more students cannot have the same pictures or materials; all work in progress is individual. Group work is encouraged for discussion purposes and clarifying ideas. CSD includes three cooperative group post-lab assignments: P3, P7 and P11, and indications will be given on how to solve them to promote individual accountability.

• Printed results from EDA tools are discussed using pens and handwritten explanations. A printed schematic or printed computer results without annotations has no value and is not marked.

• Printed graphics have white background and a preferred colour scheme. Do not waste your printer ink printing black backgrounds.

• Sections of VHDL and C language source files are printed following these indications.

• Entity names are not invented. All our specifications will include the entity names under analysis or design.

• In CSD, projects must be developed and stored in the given locations indicated in the corresponding planning section (2). Other locations will not mark. For instance, the location of the analysis of Circuit_L in PLA1_1 using Proteus is: 

 C:\CSD\P1\PLA1_1\Circuit_L\Proteus\(files, pictures, sketches, pdf, etc.)

• VHDL translations and C language source files contain comments and references to the schematics or flowcharts being translated.

• In testbenches, there is no need to print all stimulus vectors, print only a few of them and discuss the waveforms.

• Pay attention and discuss your RTL and technology schematics verifying that they are similar to your planned circuits.

IMPORTANT NOTE: If you have doubts or queries on how to solve or report something ask us questions and save much of your study time.