P_Ch1 Questions and answers	P_Ch1

Consider the discussions in this page as an addendum to your PLA assignments. This edited Q&A come from meet sessions, emails, phone calls, and class and office time with many students. Thus they have significant value and will help you to save study time. You may imagine a class-group working cooperatively in a weekly basis with the objective of solving our projects as better and faster as we can. 

 

• PLA1_1 Analysis of circuits based on logic gates (method I, methd II and method III)

Question:   I just resolved the Circuit_K using method III and checked with Proteus, when I went from the SoP to find the minterms, I had the m2 and m3 twice, I understand that in this case it doesn't affect as it is a sum of minterms. However, if it was the case that I was solving the maxterms, would it affect?

Answer:  Well, is your question about a basic property of Boole's algebra from this table?  x + x + x + x = x ?   yes. If when you try to find a list of minterms using algebra (method 3), you obtain for example: F = m1 + m4 + m5 + m4 + m1 ---->   F =  m1 + m4 + m5

In the same way, if you are generating handwritten algebraic equations and you get something like this: g = M7 · M8 · M14 · M8 · M6 · M7 ---->   g = M7 · M8 · M14 · M6

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Question: I have some doubts about the report. I have to do the Circuit_M method 2. In the report I have to do only method 2 and also method 3. Do I have to do it in 8 sheets or in 4? Do I have to put method 1 in the report?

Answer: Instructions tell you to analyse Circuit_M using method 2, this is at least 4 sheets of paper (only after having completed LAB1_1 WolframAlpha project). Instructions tell you to test/check results using method 3, this is another set of 4 sheets of paper. Method 3 is understood as another full project in itself.  

Any other project is optional. You always are invited to solve as many of them as you like; digsys contains many exercises. These additional materials can be submitted as well as part of section 1 (specifications and theory) or as annexes.

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Question:

1.-When I have the algebraic equation I can't reduce it because it comes out too big.

2.-When I have made the proteus I get three errors and I don't know why.

3.-When I have done the wolfram equation it does not give me the truth table.

Answer:

1. Step by step. Circuit_W is a section of Circuit_C, and Circuit_C is completely analysed step by step in its tutorial as a highlighted example.

2. One gate at a time and run, this is the way to find where the errors are and correct them. And also discussing your problems with other students.

3. Again, one gate/equation at a time, writing these equations in a file for combining them and running them in WolframAlpha. Learn WolframAlpha using LAB1_1 session materials.

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Question: In WolframAlpha, can I change some variables indicating what is each one in the case that I change it in the report? For example: T = A and,  X0 = B ?

Answer: Yes, if you clearly explains what you are changing and you are able to identify maxterms and minterms correctly from WolframAlpha results. Your report MUST have original symbol names. However, if possible solve all CSD exercises without modifying directories, entity, input or output names. In WolfraAlpha you can reorder expressions and even use other parenthesis styles like [ ] or { } to represent clearer expressions.

For example: logic circuit not{ not(not(X1) or [T xor Q]) or not(X0 or not (X1) ) }

You can also use mathematics language symbols instead of natural language for writing your circuit general equation, as WolframAlpha itself does when interpreting your text inputs.

For example: truth table (Q xor T) and X0   -----> truth table (Q xor T) && X0

NOT --> ~            AND --> &&             OR ---> ||

logic circuit not{ not(not(X1) or [T xor Q]) or not(X0 or not (X1) ) }  ---> 

---> logic circuit ~ ( ~ (not(X1) or [T xor Q]) or not(X0 || not (X1) ) )

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Question: I'm having some trouble on trying to extract the circuit N's truth table, I'm doing it through method 1. The point is that when I extract the truth table from simulating  on Proteus I got six minterms, but when I try to extract the truth table with the method 3 I have also six minterms but not the same from method 1. I'm trying to find the error but I just can't see it.

Answer: If you have done the processes for solving both projects is OK, your PLA will get a good mark. Now, the final result is not that important, project processes count much more. Next week you will be asked to solve the same circuit with the other two methods remaining, and in this way, you will be able to identify better where your errors are located. Or even better, talk to your team or class mates to be sure which is the sum of minterms for your circuit.

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Question: En acabar el PLA1_1 i com m'agradaria enquadernar-lo li volia demanar a veure si és possible utilitzar 13 cares (una cara per fulla) perquè quedi més net el resultat en lloc d'utilitzar 7 fulles a doble cara. Sé que el màxim són 8 fulls a doble cara però tenint en compte que el que he fet no s'excedeix, volia comprovar si és possible fer-ho.

Answer: The minimum of paper for project is four sheets, and add as many sheets as you need. For example, you may like to add as much theory, class notes or exercises as you want or as you need at section 1 accompanying the specifications. We are only asking you to prepare each project using the given four sections. And do not prepare book covers or embellishments or improvements for your submitted work. We are only interested in your draft solution and in how you are completing the process of analysing circuits. This kind of improvements, like covers, or using a word processors or Visio for pictures and schematics, is something that you will do for other courses or in your final dissertation.

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Question: We have been told to do 4 pages per method everytime we analyse a circuit. But when printing it, can we print them in both sides of the paper?  It's a very good way to reduce the amount of paper and to preserve the ink of our printers which is very expensive.

Answer: Every project section is a new sheet of paper not a page/side of paper. Don't worry now about the cost of some sheets of paper. The ink is preserved using white background, be careful to change colours in all pictures printed. Instructions are given on how to do it in ModelSim, and in any other software you can use any application for drawing to change colours and get them lighter to save ink. Most of the pictures found in digsys are examples of light/white backgrounds. Do not use word processors for writing comments on pictures or annotating, because only handwriting is accepted. Projects have four sections, but they may contain more that four sheets, for example a long development, or a project specification including also theory.

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• PLA1_2 Analysing circuits using VHDL synthesis and simulation EDA tools (method IV)

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Question: How to replace default background black colour in ModelSim wave timing diagrams?

Answer: In this EDA page there is the document explaining how to do it once ModelSim is installed in your PC.

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Question: How to eliminate vertical grid lines in ModelSim wave diagram, so that writing comments is easier and the picture cleaner?

Answer: This is how to deactivate the default grid, so that you can add your own vertical lines to indicate signal transitions or edges.

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Question: I was modifying the Circuit_W_tb.vhd file to fit my circuit. When we begin the stim_process, do we need to include all 16 combinations in it?

Answer:  Ok, follow the step-by step note guidelines indicated at PLA1_2. Lab1_2 tutorial on Circuit_W analysis must work correctly in your computer before thinking on anything else.

 No, when you start simply add two or three combinations, because the objective in this step is to check whether you can get results from ModelSim wave diagrams. When everything works fine, you can edit the testbench file again and add all the combinations because your objective is to write down the truth table.

Question: What Min_Pulse do we define? Is it up to us to decide?

Answer: Yes, any time constant is Ok. If for instance you choose Min_Pulse = 3.3 ms, you will run the simulation for 600 ms, enough time for applying all vectors.

Question: When compiling both files in ModelSim, the tb gives me an error. Is there any way to know where is it? Could it be just a semicolon? If that is the case, how do we know when to write a ':' or ';' or ',' or nothing?

Answer: This is why I ask you to follow the step-by step indications. In my testbench for Circuit_W there is no errors. Thus you simply study and adapt vectors and everything else from another similar example. In this way, there is no need to pay that much attention to VHDL syntax.

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• PLA2 Designing circuits using single-file (flat) plan A and plan B

Question: I'm attaching in this email my VHDL file, it tells me that I have to buffer the CHs, what command allows me to change the CHs to buffers? Another issue is that I don't know if I have the VHDL right, can you tell me where it would be wrong or what I can improve?

Answer: 1) Run the projects and and study our lab2 materials in your computer, and only when everything is working fine, start thinking in PLA2 specifications. 2) Study several examples of plan A and plan B circuits from out lessons and tutorials in DIGSYS. 3) Study circuit symbol, truth tables and timing diagrams (section 1 : specifications). 4) Propose an schematic/flowchart/diagram(etc for your design in paper, and if you have questions on how to translate it to VHDL, show us your schematics in emails or meet sessions or even better attending our lectures. In CSD, VHDL files are only direct translations of your diagrams and schematics, there is no need to discuss VHDL files.

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Question: My doubt is if I need to add the case where D = '0' in the testbench, or just with D = '1' is okay?

Answer: In a DeMUX the idea is demultiplexing or distributing  data or information, and this is both, '1' and also '0'. Data may be a stream of bits from sensors, telephonic conversations, digital music or CLK signals.

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Question: I am working on Plan B and developing my VHDL file of my DeMUX_16. I was wondering if I am understanding properly the way this demultiplexer works, in terms of assigning outputs. I am attaching you my DeMUX_16.vhd file.

Answer: This is a design process. Understanding the DeMUX is theory (section 1) and you can found it in class lessons. Study for instance this lesson L2.2. You cannot even think about VHDL translations like the one you are attaching here, without a plan in a sheet of paper (section 2 ---> planning your project), which was learned in LAB2. You must complete it successfully in your computer before imagining solving PLA2. So, firsts things first: if you find something in classes or lab tutorials that you do not comprehend, tell us and we will answer as soon as possible. Only in this way is conceived a translation to VHDL.

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• PLA3 Designing an arithmetic circuit using plan C2:

Question: I'm currently working on the PLA_3 and we have an error which we cannot find a solution for. We are doing the Int_Comp_16bit and to do so we adapted the VHDL files from the Int_Comp_8bit. When we run the simulation it works fine, but there is a problem with a few values. There is a photo attached as a file below. When we input the value -14600 the program stops working and represents the wrong output. We tried changing the -14600 for a different input (-15623) but the problem persists.  We've checked the code and can't find any mistakes, is there any way you could help us? I tried sending you the VHDL files but the email won't let me do it, if it's fine with you, could I upload it to Google Drive and share it with you?

Answer: First of all, change your ModelSim colours, you were given clear indications by PLA1_2 (colours). Back background is not admitted because it is a waste of ink. As you know, because we repeat it all the time in every class, when asking questions you must show your paper/draft  truth tables, symbols, timing diagram, plans, schemas, ideas, etc. because all the errors came from misunderstandings or some connections wrong in schematics (specifications & planning). Development and test is a translation of your paper work from adaptations and similar projects found in our company "CSD", it is automatic and generally do not generate errors. So, there is no need to attach VHDL files or results because you can check whether look like your sketches. So, send schematics or something in paper if you have questions. You don't have to check your "code", it doesn't exist in Chapter 1 and Chapter 2, we have only hardware schematics; programming code will be for Chapter 3.

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Question: How many pages does PLA3 have to contain? If it is 4 pages  it is only Comp_16bit and if it is 8 pages it is Comp_1bit and Comp_16bit.

Answer: As all projects, four sections. Perhaps in this project you need annexes, see our indications on the note on how to write and organise your report. Components are reported in annexes and perhaps they are projects themselves or perhaps only explanations or schematics because they are already solved in digsys and you simply copy their VHDL files.  If you invent a new component, the best way to report it is as an annex organised as a complete project.

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Question: I wanted to know if for the PLA3 Comp_4bit project we have to use plan A or we can usea any plan, because you told us for the Comp_1bit to use the plan A but I don't think you specified the plan we should use for Comp_4bit.

Answer: Comp_4bit is designed using plan C2 based on chaining Comp1_bit. It is the Comp_1bit that can be designed using plan A, B, or C2 MoM or MoD. You can find the internal sketch for Comp_4bit using plan C2 at P3 tutorials. (Note: there is also the version of Comp_4bit using plan A, but I guess that it is more complicated. It is here to demonstrate how the chip 74LS85 is build).

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Question: Do you want any special content on the video or just an explanation of how we built the Int_Comp_16bit?

Answer: Technical or professional video presentations are standardised; I am not being very specific apart from some guidelines, because probably you already had presented some projects in other subject and have got some experience by now.

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Question: Tengo una pregunta, hago el int_comp_16 MoD, me preguntaba si el Dec_5_32 se pone dentro del comp_4 o dentro del comp_1?  

Answer: Read and study about the MoD in lecture L3.3. Do not try to solve your PLA before having got some theory and having completed LAB3 tutorial exercises to copy and adapt to your PLA. If you have 5 inputs as in the case of Comp_1bit you need a Dec_5_32. And this is feasible. In you have a a Comp_4bit, as you say, you will have up to 11 inputs, requiring an impossible decoder that will have to generate 2048 outputs! (this is why not all plans are always practical).

Be aware as well and very careful with chip and entity names (and also with project folders): designing comp_1, comp_4 or int_comp_16 will mark always 0/10 (even if you are submitting a project 20 pages long). Designing Comp_1bit, Comp_4bit or Int_Comp_16bit will generate marks up to 10/10. 

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• PLA4 on gate-level measurements (how fast is a circuit calculating?)

Question: In the specifications of the PLA4, there is this task: - Demonstrate that the circuit does not calculate correctly when Min_Pulse is shorter that the circuit's propagation delay. In my case, the max propagation delay obtained from Quartus Prime is xx.yy ns and the one obtained in ModelSim with my test numbers is zz.ww ns. Just to demonstrate the results is enough? Or, do I need to create a bigger Min_Pulse than xx.yy ns and run again? 

Answer: In ModelSim you are calculating propagation delays in a given transition of the many, not necessarily the worst-case scenario. Using timing analyser you calculate all propagation delays from any input to any output, thus being able to measure the longest path. For instance tP = xx.yy ns in your case. We are asking you now to run a gate-level ModelSim simulation considering a constant Min_Pulse <  tP so that you are forcing your circuit to switch faster than it can, and probably you will see on ModelSim waves that outputs are not reaching stable values with correct calculation results.

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Question: Concerning the report of PLA4, can we reuse the same report as in PLA3 adding the fifth section (gate-level simulation)?

Answer: Well, yes, optionally, you can photocopy the 1-2-3-4 report from LAB3, modify something if you need it, from the given feedback or perhaps because your PLA3 was not yet fully working, and then add your design step 5 (individual). At least two sheets, because you are working with two new tools: gate-level  simulation in ModelSim and Quartus Prime timing analyser. But, before anything else, you have to ask and discuss these report ideas and details with your lab instructor. Study and develop all the LAB4 project in your computer before starting this PLA4.

 

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