Lecture 2 
L2.2: Designing standard logic circuits using VHDL. Multiplexers, demultiplexers [P2] Flat (single VHDL file) plans: structural plan A / behavioural plan B, 
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1.7.2.2. Design examples (our list of design strategies)
Alternative ways to invent circuit architectures in VHDL:
Plan A) Structural (flat)  one VHDL file using equations
Plan B) Behavioural (flat)  one VHDL file using the truth table or algorithm
Plan C1) Structural (hierarchical)  describing a hierarchical structure in a single VHDL file (complicated/not recommended).
Plan C2) Structural (hierarchical)  several VHDL files using COMPONENTS, SIGNALS and logic equations. This modular approach is the best at CSD introductory level to design large circuits. Introduced in next P3.
1.7.3. Demultiplexers or data distributor
Specifications Design a DeMUX_8 circuit.
Example of MUX_DeMUX.pdsprj circuit simulation.
What is the application of a DeMUX_n? The idea is to send date from a single source to different destinations.
Fig. 1. Typical application oof data distributors. 
1.7.3.1. DeMUX_4, DeMUX_8, etc.
Specifications Design a DeMUX_8 circuit.
What is the symbol and circuit's truth table of a DeMUX_16? Draw a timing diagram. Find an example commercial chip.

Fig. 2. DeMUX_8 symbol and truth table. 
Plan
1.7.3.2. Design examples using plan A and plan B.
Several circuits can be implemented depending on the plan. For example:
 Plan A: examine the truth table and deduce the equation equations using ones, which is much easier and practical than writing the equation using zeros. Or, instead, write the truth table in this file DeMUX_8.tbl and run minilog to find directly the SoP for each output.
 Plan B: capture the circuit's algorithm in flowcharts or the truth table schematic as in Fig. 3 into VHDL and synthesise the project using FPGA EDA tools for a target chip.
Fig. 3. Example schematic ready for VHDL. We do not povide equations or circuits, but simply translate the full truth table using VHDL statement. The synthesiser will find a circuit using FPGA resources (logic elements). 
Development
Plan A For instance, using the truth table canonical equations based on minterms we can easily draw its circuit as shown in Fig. 4.

Fig. 4. DeMUX_8 canonical equations and circuit representation. 
Now it is easy to translate this circuit in Fig 4 into a VHDL file DeMUX_8.vhd ready for synthesis using FPGA EDA tools.
Plan B Transate the schematic in Fig. 3 into VHDL (DeMUX_8.vhd file) and syntesise it for a given target chip using FPGA EDA tools such Quartus Prime.
Test
Use a VHDL testbench (DeMUX_8_tb.vhd file) in ModelSim to verify that the demultiplexer works as expected in Fig. 2.
Fig. 5. Timing diagram demonstrating how the circuit works. 
Or instead, capture the developed circuit based on logic gates in Fig. 4 in Proteus for a given classic technology (CMOS or LSTTL) and run simulations.
1.7.3.3. DeMUX expansion circuits (plan C2)
For instance, how to invent a DeMUX_32 using small chips of the same kind?
 Draw the truth table of our DeMUX_32 symbol.
 Propose its internal architecture using DeMUX_8 components and other circuits if necessary.
1.7.3.4. Commercial chips
The chips 74HCT138 can operate as a demultiplexer.
 Draw the truth table of our DeMUX_8 symbol (Fig. 2).
 Study the chip's truth table from its datasheet.
 Propose its internal architecture using only the 74HCT138 chip and logic gates if necessary (plan C2).
 Capture and simulate your circuit in Proteus (method II) to demonstrate that it works as expected.
The chip 74HCT154 can be used as a demultiplexer.
 Draw the truth table of our DeMUX_16 symbol.
 Study the chip's truth table from its datasheet.
 Propose its internal architecture using only the 74HCT154 chip and logic gates if necessary (plan C2).
 Capture and simulate your circuit in Proteus (method II) to demonstrate that it works as expected.
Exercise: Plan A. Write the truth table of the MUX_4 symbol represented in Fig. 6. Find the following two equations and the corresponding logic circuits: (1) using ones and ANDORNOTBuffer logic gates; (2) using zeros and only NOR2 gates. You can test your development using method II or method IV.

Fig. 6. MUX_4 symbol. 