UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

L1.6

Lecture 1

L2.1: Designing standard logic circuits using VHDL. Multiplexers

[P2] Concept map associated to combinational circuits design. VHDL design flow

L2.2

[19/2]

 1.7. Standard combinational logic circuits

Once we have understood P1 basic ideas on Boole's algebra and circuit analysis and design using logic gates, let us continue presenting basic standard combinational blocks.

1.7.1. Concept map (for all standard circuits in P2, P3 and P4)

All combinational circuits (including arithmetic circuits in P3 and P4) are organised following this concept map in Fig. 1 and Fig. 2 rec.

1.7.1.1. Truth table, symbol, timing diagram

1.7.1.2. Chip expansion, enable input

1.7.1.3. Examples of commercial chips

Concept map
Fig. 1. Concept map for organising circuit specifications. (Visio) 

 

1.7.1.4. VHDL design plan (our list of design plans: plan A, plan B and plan C2

planning the design using VHDL tools
Fig. 2. The three CSD strategies for planning circuits. Plan C1 is left only for designing FSM in P6.

The concept map includes our VHDL design flow (Visio) for EDA tools that ends donwloading the configuration file into the programmable chip.

1.7.2. Multiplexers or data selector

1.7.2.1. MUX_2, MUX_4, MUX_8, etc.

Specifications: Design a MUX_8

Theory and applications. What is a MUX or data selector? Play with this example of MUX_DeMUX.pdsprj simulation. The full prototype is at LAB2.

MUX-DEMUX

MUX

Demux
Fig. 3. MUX-DeMUX application examples (source: ref. 1, ref.2, ref. 3).

Symbol, truth table, special inputs, example of timing diagram, commercial circuits.

MUX function and symbol
Fig. 4. MUX_n circuit.

The symbol and truth table example for an 8-channel multiplexer (MUX_8) is represented in Fig. 5.

Symbol

Truth table
Fig. 5. MUX_8 symbol and truth table.

This timing diagram in Fig 6 is an example on how the signals evolve in time.

timing diagram
Fig. 6. Timing diagram example.

 

Full planning, development and testing is presented at LAB2 as design tutorials on plan A and plan B using our VHDL EDA tools (minilog, Quartus Prime, ModelSim, etc.).

Plan A using equations and logic gates.

Is it possible to draw a canonical circuit based on product maxterms or sum of minterms?

Canonical representation

Fig. 7. Discussion on whether is possible to infer canonical logic equations based on maxterms or minterms.

Thus, canonical circuits based on maxterms or minterms are not practical. We will try to find simpler equations like SoP or PoS. We have two alternatives: simplifying inspecting the truth table in Fig. 5 above, or minimising using minilog (as done in Lab2).

Equations using SoP

MUX_8 circuit using SoP

Fig. 8. Truth table simplified using all the '1' terms (products) and writing them as SoP. Equivalent logic circuit requiring 8 AND-5 gates and another OR-8 gates.

In the same way, we find a simplified equation inspecting the truth table and anding all the '0' terms (sums) in the form PoS, as shown in Fig. 9.  

PoS

Circuit MUX_8 using sums

Fig. 9. Equations and circuit using OR-5 gates (sums) and a final AND-9 (product) (PoS). Equivalent logic circuit.

 

 Plan B. Additionally and alternatively, we can "write the circuit", interpreting the truth table as an algorithm or flowchart that describes its functionality or behaviour.

High-level algorithm

Fig. 7. High-level definition of the MUX_8 truth table.

1.7.2.3. MUX expansion circuits

Expanding circuits of the same kind is like applying our plan C2. For instance:

- How to build a MUX_16 using MUX_4 components?

- How to invent a MUX_8 using only MUX_2 components?

 

1.7.2.4. Commercial chips

74HCT151, 74HCT152, 74HCT153, etc. 

 

Exercise: Draw the truth table of the DeMUX_16 represented below. How long is the truth table? Find its equations.

DeMUX_16

Fig. 10. DeMUX_16 symbol.