UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL



P_Ch2 Questions and answers


Consider the discussions in this page as an addendum to your PLA assignments. This edited Q&A come from meet sessions, emails, phone calls, and class and office time with many students. Thus they have significant value and will help you to save study time. You may imagine a class-group working cooperatively in a weekly basis with the objective of solving our projects as better and faster as we can. 


Question: In the specifications of the PLA4, there is this task: - Demonstrate that the circuit does not calculate correctly when Min_Pulse is shorter that the circuit's propagation delay. In my case, the max propagation delay obtained from Quartus Prime is xx.yy ns and the one obtained in ModelSim with my test numbers is zz.ww ns. Just to demonstrate the results is enough? Or, do I need to create a bigger Min_Pulse than xx.yy ns and run again? 

Answer: In ModelSim you are calculating propagation delays in a given transition of the many, not necessarily the worst-case scenario. Using timing analyser you calculate all propagation delays from any input to any output, thus being able to measure the longest path. For instance tP = xx.yy ns in your case. We are asking you now to run a gate-level ModelSim simulation considering a constant Min_PulsetP so that you are forcing your circuit to switch faster than it can, and probably you will see on ModelSim waves that outputs are not reaching stable values with correct calculation results.

Question: Concerning the report of PLA4, can we reuse the same report as in PLA3 adding the fifth section (gate-level simulation)?

Answer: Well, yes, optionally, you can photocopy the 1-2-3-4 report from LAB3, modify something if you need it, from the given feedback or perhaps because your PLA3 was not yet fully working, and then add your design step 5 (individual). At least two sheets, because you are working with two new tools: gate-level  simulation in ModelSim and Quartus Prime timing analyser. But, before anything else, you have to ask and discuss these report ideas and details with your lab instructor. Study and develop all the LAB4 project in your computer before starting this PLA4.


Question: SD input in this circuit is working as `1´ in every chip, right?


Answer: SD is active high. It means that when SD = 1 --> Q = 1 immediately. Like CD that is also active high. I guess so that when you click SD --> P(4..1) = "1100" and when you click CD --> P(4..1) = "0000" . And because those are latch asynchonous inputs, you cannot click them both at the same time.

Question: In Circuit_D there is this double inverter in the T_FF(Chip0).  Does this mean that when signal P3 goes to the first inverter, 1 clock cycle goes and then after the 2 clock cycle it arrives to the CLK of Chip0? Or does the signal P3 go directly to Chip4 in the same CLK cycle?


Answer: In the same CLK period or cycle as you say, just after the CLK rising edge. In principle, when P3 switches logic values because of a Chip3 CLK edge, P3 propagates through two inverters (2·tP) before reaching the Chip0's CLK, that will make it possible to toggle P4. All this in the same CLK period. CLK period may be 1 ms, and the switching phenomena is on ns range.

Question: I copied your Circuit_async.vhd and Circuit_async_tb.vhd, but my Q isn't working, I tried put values into Q but it still not working.


Answer: We tell you always the same procedure: (1) Solve a project of only one FF (if possbile with the three analysis methods), to learn the theory as well. (2) Solve the project consisting of two FF to comprehend what is this complication of having two CLK in the same circuit. (3) Solve the three tutorials in LAB5, and keep trying until it works as reported in the web page. Use paper to draw your circuits, to see better what is happening and how the circuit is translated for example to Proteus or into VHDL. (4) Start with your assigned PLA5. There is no other way to learn these materials so that you can also solve similar circuits in exams.

By the way, you cannot copy our Circuit_async_tb.vhd. You can copy our circuit translation Circuit_async.vhd, but never the testbench file. The mechanics that we repeated always in Chapter 1 was: Generate your testbench skeleton from Quartus Prime, move the file to the folder project and rename it. And with the help of our example _tb.vhd in the web: - Add the constant (Min_Pulse, or CLK_Period, now in Chapter 2) - Add the stimulus process - Run functional simulations. - Run gate-level simulations.

Question: Where to find this component RS_FF that has both SD and CD in VHDL for solving circuits using method 3?

Answer: It is located at P5, tutorial on JK_FF. Instead of an RS_FF you can use the JK_FF

Question: What do you mean when in the LAB5 method 3 you ask for how many states does the circuit have?

Answer: The question is for any analysis method: how many different outputs you can generate with your circuit? For example, Circuit A has P(4..1) as 4-bit vector output, so, how many different binary numbers the circuit generates in time? If you solve later on a similar synchronous circuit using the FSM method, each generated number will correspond to an internal state.

Question: This error is from ModelSim when I try to simulate my circuit using method 3, what is the meaning?

image error

Answer: Your circuit has to be Circuit_B.vhd, not another name. And apart from this detail, it is difficult to see what is the problem. And so, we have to start discussing inspecting your plan in paper. How it is looking like? We recommend you to use our circuit JK_FF.vhd as a component for all chips in your design Circuit_B, it contains CD and SD. And, as usual, before translating you have to draw your circuit B in a new sheet of paper annotating all signals of interest, for example in the picture below. Check your RTL, check that your circuit contain 4 registers. Drive in the test bench only CD, and later on, after many CLK periods, drive your SD, but never at the same time. Etc.

 Circuit_B plan

Question: How to organise the report, it is a project or two projects?

Answer: Like in P1 analysis. If you have to analyse the circuit using two methods, this s two projects. (1) is practically the same: write the specifications one time and photocopy it. (2) Plan depends on the method. (3) the objective is to determine the timing diagram and how many states the circuit will contain, what binary numbers are generated. (4) is a paragraph discussing whether you got the same results or not, and what may be the reason.

The key point here is the step-by -step plan. (A) solve a circuit (any circuit) with only one FF, draw its timing diagram, explain what values are sampled and when, and when the outputs changes. Tutorials D_FF, T_FF and JK_FF can help. (B) Try to solve a circuit (any circuit) that has two CLK signals. name all the circuit signals of interest. What values are sampled by which signal and when? What codes or how many states are generated? Apply all you learned in step A. (C) Now, try to solve your assigned circuit.


Question: I can't find where the Johnson counter and the Gray code are.

Answer: Well, all these binary codes: radix-2, Gray, one-hot, Johnson, etc., are standard binary codes used in many applications. Google these names and you will find pages with information.

Question: I don't know how to do the CLK process. I deduce that the counter Johnson putting four T_FF in series, since it is what I have found on the internet as you can see in this image. I also have the doubt of whether the program in VHDL have to do it with chips D_FF or T_FF.


Answer: If you have to design a Johnson counter using our FSM approach, you may use internet for finding simply what is the Johnson code and so determine  what outputs are generated at each state. In this way you will fully comprehend the specifications of the application that you are designing. Inventing circuits in CSD is 1-2-3-4-5 as usual, and in this case, applying our FSM method from a) to n). And all of this, as you can guess, only after having completed LAB6 reference tutorials and studied P6 highlighted project, because PLA6 is simply a systematic repetition and adaptation.

Question: Where to find the information on the number of D_FF used in the design if the target chip is MAX II?

Answer: You can find it in a summary file generated by the analysis and synthesis process:

Number of registers

Question: I have a question about Timing Analyzer. I did all of the simulations and I am not sure if my results are correct because the report datasheet is not similar to the one we did in previous projects. Is it because I made a mistake or is it correct?

timing analyser results

Answer: Yes here in Chapter 2 we are not that much interested in propagation delays of gates tP from any input to any output as we were in Chapter 1, but now our interest relies on "how long does it take to change outputs synchronously with CLK rising edges".

It seems ok, what I do is simply swap the columns in the spreadsheet: from CLK port to output data port because the meaning is clearer. It says that tCO = 6.8 ns, meaning that you can speed up your system CLK up to a maximum frequency of 147 MHz and the digital system is still working correctly.


Question: Our assignment is to built the roulette using shift registers, I want to understand more how to implement this kind of circuit because reading the indications are not clear.

Answer: The more time you spend on specifications the better. Study what is a shift register, for instance  from this tutorial Shift_reg_4bit. Imagine the circuit from this perspective at the specifications level. Here, in your application, one key idea is how to expant it, the same approach that we used for Counter_mod16 and building larger counters. Study and find information on roulettes, the simplest ones, what kind of buttons and outputs they have, how they work.

You can use this shift register to invent using plan C2 a larger one (chip chaining or chip expansion). And then, I guess that the idea of a roulette is loading in parallel a single '1', and rotate it at high speed, for example meanwhile the player is pressing the button "play". Probably, when releasing the button, the '1' will be saved in anyone of the numbers. Or something like this to start. This project can be used as an starting point for discussing the generation of random numbers using digital circuits or computers.

Question: Discussing about the clock generator in the Counter_BCD_mod24, where do you want us to put it in the report and what do you want us to show about it?

Answer: You may think about a Counter_BCD_mod24_top that includes other components like CLK_Generator and (optionally) Hex_7seg_decoder if you like to present results in 7-segment displays. Something like this. As you see in P8 Timer highlighted project, CLK_Generator is designed internally as a component in an annex.

Question: I would want to ask about the Data_Reg_20bit, do we have to use the PlanY or PlanC2 using components such  Counter_mod16?

Answer: If you have to invent large counters or large data or shift registers, it is better to use basic components like Counter_mod16 or Data_reg_4bit or Shift_reg_4bit, already solved in Digsys P7, and learn how to chain or expand them to design larger modules of the same kind, this is studying for exams at the same time that solving PLA7. But it it up to you, you can choose.

Question: I'm wondering if it is correct to use a Counter_mod16 and truncate it to 9? I mean, doing this:  Digit tens: 0,0,0...,0,0, 1,1,1,1,...1,1,1,..., 5,5,5,...,5,5,5,0,0... Digit units: 0,1,2...,8,9, 0,1,2,3...,7,8,9,..., 0,1,2...7,8,9,0,1... So that when the digit arrives to 59 changes to 00.

Answer:  Which PLA7 circuit was assigned to your group? Read and study in detail diagrams and ideas solved in class and available in digsys lessons and tutorial examples, because many times we have already discussed these ideas and probably you have classnotes. If your question is on counter chaining and truncation, it was at lecture L7.3 where we studied in detail these concepts, and for instance P7 highlighted project shows you many details, pictures and diagrams. Probably your PLA7 is a simple repetition and adaptation on what is covered in class; this is why attending classes is such crucial in CSD.

Question: Regarding the video we are facing a slight problem with the duration, as it is a quite long project. We try to explain our design in the blackboard, the transition to VHDL code, Quartus synthesis, functional and gate-level simulation, etc.; the video gets a little bit longer. Is it okay if we exceed the time limit of 10 min?

Answer: This is a very good question, thank you. Well, this is the point. There is no need to explain everything. Oral presentations aim to be succint and brief, focused on main points and ideas. Doctoral thesis may be abstracted in 10 min. if required. Presentations of scientific papers in most conferences are not much longer. Technical reports, on the other hand, may be as long and detailed as necessary (so that other engineers can repeat and validate or refute the experiments). The question is: how to explain my complex design work in 7 min to a technical audience? (7 minutes is ok because you are only two members)