UPC EETAC Bachelor's Degree in Telecommunications Systems and Network Engineering EEL

AR1

Lecture 2

L5.2: RS flip-flops

[P5] On the internal architecture of an RS flip-flop, CLK and clear direct (CD) concepts

L5.3

[3 Nov]

2.3. Flip-flop. Synchronous 1-bit memory cell

Flip-flops are basic building blocks for digital systems. They are documented everywhere.

2.3.1. The concept of the CLK signal. Synchronicity.

In a digital system, outputs (Y) and internal states (S) update to the future value only on the CLK's rising edge transition, this is the idea of synchronicity or a synchronous digital system.

Digital CLK oscillators generate rectangular signals for running digital systems. One rising edge per period.

CLK circuit waveforms

2.3.2. CLK distribution.

2.3.3. CLK circuits

2.3.2.1. RC circuit

2.3.2.2. Integrated circuit 555 oscillator

2.3.2.3. Quartz crystal oscillator

 

2.3.4. The concept of clear direct (CD), asynchronous reset or master reset.

In a digital system, time starts when turning ON the power supply at t = 0. System internal state (S) and outputs (Y) remain undetermined, unknown or unpredictable until a reset or clear direct (CD) button is clicked at t = t1. While CD is set high, the systems remains at its initial state. Once CD is low, the system starts updating outputs (Y) and internal states (S) after each CLK's rising edge.

CLK and reset signals

2.3.5. Automating system initialisation: power-ON reset.

Power-ON reset concept

2.3.6. Standard flip-flops

In the previous lesson, we studied asynchronous latches RS_latch and D_latch.

Latches

Now we can present common types of synchronous flip-flops, 1-bit memory cells: RS_FF, D_FF, JF_FF and T_FF .

Flip-flops

Flip-flops

2.3.6.1. RS flip-flop (RS_FF)

2.3.6.1.1. Function table, state diagram, timing diagram

Run the "RS_FF.pdsprj" example in Proteus to grasp differences with respect to a latch. What is the meaning of sampling input values?

RS_FF timing diagram

2.3.6.1.2. Deducing RS_FF from RS_latch, CLK's rising-edge detector

Proposing an RS_FF circuit from plan A: how to deduce an RS_FF from an  RS_latch?

1. RS_latch operation

RS_latch

Rslatch

2. From RS_latch to gated RS_latch

Gated RS_Latch

3. Edge detector circuit to convert the CLK input into an enable signal input

Edge detector

4. From gated RS latch to RS_FF

RS_flip_flop

RS_Flip_flop

This is an idea on how a CLK rising edge can trigger the sampling of inputs. Other circuits are proposed in the literature, for instance, master-slave configuration.

Fortunately, we describe these components using a much simpler, easier and repetitive behavioural approach (in plan C1 and plan B), leaving synthesis of memory cells in the FPGA fabrics to EDA tools. These are our flip-flop reference projects: D_FF, JK_FF, T_FF.

 

2.3.6.1.3. Commercial chip

A classic chip is HEF4027B. 

 

Activity #1: An RS_FF is driven by the following waveforms. Deduce and explain the output signal.  

Waves

 

Activity #2: Analyse the following RS_FF applying its function table.

Waveforms