UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

L11

Lecture 1

 L12.1: Adapting dedicated processor applications

[P12] Project 18.5 s fixed-time timer. FSM + datapath()

L12.2

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3.7. Dedicated processors in C (datapath, control unit )

3.7.1. Hardware-software diagram

3.7.2. Examples

3.7.2.1. Timer (design phase#1)

Circuit developed and tested in Lab11.

What are the especifications of a timer? What is the meaning or triggering and re-triggering?

Reviewing the project of a programmable timer using VHDL (Chapter II and dedicated processors (P8).

What is the difference if the timer timing period is ns, ms, minutes or weeks?

- Hardware. External CLK time base (INT1) and trigger button (INT0).

- Software. FSM controlled by the trigger button (INT0). Datapath (counter RAM variable) enabled only when required.

 

3.7.2.2. Timer_LCD (design phase#2)

Enhance the fixed-time Timer of 18.5 s with an LCD, so that ASCII messages can be represented to indicate how the system operates.

Circuit developed and tested in Lab11.

3.7.3. Examples: event counter

3.7.3.1. Tachometer, speed meter, odometer

 

 

Exercise: Find in the PIC18F4520 datasheet the TMR0 schematic. Configure the bits for generating a 1780 ms timing period.