Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC

Digital Circuits and Systems (CSD) planning by weeks and sessions

Chapter 1: Combinational circuits	Week 1	Week 2	Week 3	Week 4	Week 5
		PLA1	PLA2		PLA3_4
					Q#1.1

Fig. 1. Symbol of a generalised combinational circuit. This block is described by its truth table or the equivalent canonical equations product of maxterms or sum of minterms.

Chapter 2: Sequential systems	Week 5	Week 6	Week 7	Week 8	Week 9
		PLA5_6		PLA7_8
		Q#1.2		Q#2.1

Fig. 2. Internal architecture of a finite state machine as studied in CSD.

The state register contains a bank of r D_FF memory cells.

This FSM will be implemented in a single VHDL file.

Chapter 3: Microcontrollers	Week 9	Week 10	Week 11	Week 12
		PLA9_10			P_Ch3
		Q#2.2		Q#3.1


	Fig. 3. Adapting the structure of a FSM to the software environment in C language. Our programming style and code organisation will mimic concepts studied in previous chapters.

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