Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC

Digital Circuits and Systems (CSD) planning lectures and labs

Chapter 1: Combinational circuits (lab timeline)
L1.1	L1.2	L2.1	L2.2	L3.1	L3.2	L4.1	L4.2
LAB1.1	LAB1.2		LAB2		LAB3		LAB4
P_Ch1	SP1.1		SP1.2		SP1.3		SP1.4
							Q1-4

Fig. 1. Symbol of a generalised combinational circuit. This block is described by its truth table or the equivalent canonical equations product of maxterms or sum of minterms.

Chapter 2: Sequential systems
L5.1	L5.2	L6.1	L6.2	L7.1	L7.2	L8
	LAB5		LAB6		LAB7
	P_Ch2		SP2.1		SP2.2
						Q5-8

Fig. 2. Internal architecture of a finite state machine as studied in CSD.

The state register contains a bank of r D_FF memory cells.

This FSM will be implemented in a single VHDL file.

Chapter 3: Microcontrollers
L9	L10	L11	L12
LAB9	LAB10	LAB11
P_Ch3		SP3.1
			Q9-12


	Fig. 3. Adapting the structure of a FSM to the software environment in C language. Our programming style and code organisation will mimic concepts studied in previous chapters.

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