L2.1 Lecture 2

L2.2: Designing standard logic circuits using VHDL. Multiplexers, demultiplexers [P2] Flat (single VHDL file) plans: structural plan A/ behavioural plan B

L2.3 [20/9]

1.7.2.2. Design examples (our list of design strategies)

Alternative ways to invent circuit architectures in VHDL:

Plan A) Structural (flat) - one VHDL file using equations. Used from P1.

Plan B) Behavioural (flat) - one VHDL file using the truth table, algorithm or flowchart.

Plan C1) Structural (hierarchical) - describing a hierarchical structure in a single VHDL file (complicated and not recommended- We will use it only in P6 to describe a FSM in a single file).

Plan C2) Structural (hierarchical) - several VHDL files using COMPONENTS, SIGNALS and logic equations. This modular approach is the best at CSD introductory level to design large circuits. Introduced in next P3. 

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1.7.3. De-multiplexer or data distributor

Specifications Design a DeMUX_8 circuit.

What is the application of a DeMUX_n? The idea is to send date from a single source to different destinations.  Example of MUX_DeMUX.pdsprj circuit simulation.

Fig. 1. Typical application of data distributors.

1.7.3.1. DeMUX_4, DeMUX_8, etc.

What is the symbol and circuit's truth table of a DeMUX_16? Draw a timing diagram. Find an example commercial chip.

Fig. 2. DeMUX_8 symbol and truth table.

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Plan

1.7.3.2. Design examples using plan A and plan B.

Several circuits can be implemented depending on the plan. For example:

- Plan A: examine the truth table in Fig. 2. Deduce the equations using ones (minterms), which is much easier and practical than writing the dual equation using zeros (maxterms). Or, instead, write the truth table in this file DeMUX_8.tbl and run minilog to find directly the minimised SoP or PoS for each output.  Test your circuit using methods II or III.

- Plan B: capture the circuit's algorithm in flowcharts or the truth table schematic as in Fig. 3. Translate into VHDL and synthesise the project using FPGA EDA tools for a target chip (as in LAB1.2 or LAB2 tutorials. Test the circuit using a VHDL testbench.

Fig. 3. Example schematic ready for VHDL. We do not povide equations or circuits, but simply translate the full truth table using VHDL statement. The synthesiser will find a circuit using FPGA resources (logic elements).

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Development

Plan A For instance, using the truth table canonical equations based on minterms we can easily draw its circuit as shown in Fig. 4.

Fig. 4. DeMUX_8 canonical equations and circuit representation.

If you like to check the equations that you have inferred simply inspecting the truth table, you can run minilog using this DeMUX_8.tbl file containing the circuit's truth table.

Fig. 5. List of SoP and PoS equations from minilog.

Now it is easy to translate this circuit in Fig 4 into a VHDL file DeMUX_8.vhd ready for synthesis using FPGA EDA tools.

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Plan B Transate the schematic in Fig. 3 into VHDL (DeMUX_8.vhd file) and syntesise it for a given target chip using FPGA EDA tools such Quartus Prime.

 

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Test

Let us use a VHDL testbench fixture to apply signals or stimulus and test how the circuit works.

Fig. 6. Testbench fixture for testing the designed entity.

Use a VHDL testbench (DeMUX_8_tb.vhd file) in ModelSim to verify that the demultiplexer works as expected in Fig. 2.

Fig. 7. Timing diagram demonstrating how the circuit works.

Or instead, capture the developed circuit based on logic gates in Fig. 4 in Proteus for a given classic technology (CMOS or LS-TTL) and run simulations.

 

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1.7.3.3. DeMUX expansion circuits (plan C2)

For instance, how to invent a DeMUX_32 using small chips of the same kind?

- Draw the truth table of our DeMUX_32 symbol.

- Propose its internal architecture using DeMUX_8 components and other circuits if necessary.

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1.7.3.4. Commercial chips

The chips 74HCT138 can operate as a demultiplexer.