|
Bachelor's Degree in Telecommunications Systems and in Network Engineering |
|
|
Laboratory |
Lab 1.2: analysis method III on EDA tools: VHDL synthesis + simulation + FPGA prototype This is the highlighted reference Circuit_C [P1] for practising with analysis methods |
[26/9] |
|
This is the individual post lab assignment PLA1_2 to be submitted next Lab 2 session. Study in detail and execute in your computer this lab tutorial and the reference design before attempting to solve the PLA. |
1.4.3. Analysis method III using VHDL synthesis and simulation EDA tools
Before advancing towards P2 on the design of standard combinational circuits using VHDL tools, let us discover how to solve the last P1 analysis method III rec. using VHDL language and electronic design automation EDA tools to synthesise and simulate a circuit with the aim of deducing its truth table.
NOTE: Students must install software EDA tools in their personal computers. We will supply software editions and licences.
| 1. Specifications | Planning | Developing | Testing | Report | Prototype |
Find the truth table of Circuit_W represented in Fig. 1 using VHDL synthesis and simulation tools.
|
|
| Fig. 1. Symbol and internal architecture of Circuit_W to be analysed. |
Draw an example of timing diagram showing how to drive inputs, so that the truth table (circuit output) can be deduced using a VHDL testbench in ModelSim tool.
|
|
| Fig. 2. Example timing diagram showing some input combinations and how they can be translated into a VHDL file. In this project we must run the simulation for all the input combinations to be able to deduce the circuit's truth table. |
| Specifications | 2. Planning | Developing | Testing | Report | Prototype |
The plan requires, as in method IV (WolframAlpha) or method I (algebra), obtaining the circuit's equation that this time will be translated literally to VHDL.
Part I: circuit synthesis
- Find a similar file to copy and adapt. For example from this EDA tutorial on Quartus Prime installation. Rename and save it as Circuit_W.vhd at this project location:
C:\CSD\P1\Circuit_W\VHDL\(files)
- Translate your circuit equation into VHDL using the Notepad++ enriched editor.
- The tool for synthesising the equation will be Intel Quartus Prime. The tool for simulating the circuit will be ModelSim Intel Starter Edition. Select an Intel target chip, for example, the CPLD MAX II EPM2210F324C3 chip.
|
|
| Fig. 3. Initial ideas on planning the solution. Add many more details on the sequence of steps required to obtain the final truth table. Explain also the concepts involved in this flow. |
- Start a Quartus Prime project and synthesise the circuit.
- Examine, print and discuss the RTL schematic.
- Examine and discuss the technology schematic. How many resources from the FPGA are used in this circuit?
Part 2: circuit simulation to be developed in the second part of this laboratory session below:
- Draw a VHDL testbench fixture for the chip under test. In two steps:
-
Generate an skeleton testbench in Quartus Prime. Move it to the project folder and rename it as Circuit_W_tb.vhd
-
Complete the stimulus process with some input activity, for example with some signals from Fig. 2.
- Run the simulation and examine the wave analyser results.
- Complete all the combinations and write down the circuits truth table.
- Check the truth table comparing results from other methods.
| Specifications | Planning | 3. Developing | Testing | Report | Prototype |
Part 1: Circuit synthesis
Start obtaining the equivalent circuit equation using paper, as in Fig. 4.
|
|
|
Fig. 4. Analysis gate by gate in order to find the equivalent algebraic equation. |
NOTE: Use in CSD the Notepath++ enriched text editor, a very convenient free tool for writing VHDL and C files. Another free enriched editor is Scriptum from the company HDL Works.
Find a similar file to copy and adapt. Rename and save it as Circuit_W.vhd at this project location: Translate your circuit equation into VHDL using the Notepad++ enriched editor.
|
|
| Fig. 5. Project location and file name. |
This is a VHDL source file example Circuit_W.vhd..
|
|
| Fig. 6. Example of circuit description printing and indications. |
Start a new synthesis project targeting a commercial programmable logic device (PLD) or field programmable gate array (FPGA) chip. Here you have several devices available in our labs for experimentation. For instance, let us select an Intel CPLD MAX II EPM2210F324C3 chip.
-
Project name: Circuit_W_prj
-
Top entity: Circuit_W
|
|
| Fig. 7. Quartus Prime new project wizard. Pick up for instance a MAXII, MAX10 or Cyclone target chip. |
Run the circuit synthesis flow to obtain the circuit.
|
|
| Fig. 8. Synthesis, start compilation top icon and final summary indicating zero errors. |
Represent your circuit visualising the RTL schematic (ideal) and also the technology view (real).
|
|
| Fig. 9. Tools for visualising the circuit synthesised. |
Print the circuits using snipping tool (or any other similar tool like Snagit from TechSmith). Discuss differences between the two schematics. How many resources are used (logic cells or macrocells)?
|
|
| Fig. 10. RTL example picture. |
Finally, as shown in Fig. 11, the real circuit is synthesised in a single LUT cell using SoP equation minimised by Quartus Prime.
| |
| Fig. 11. Technology view when targeting a MAX II chip. |
It is a good time to browse the MAXII datasheet and figure out some target chip details. How many resourses are used in this synthesis? What is a logic element? What is a look-up table (LUT)?
|
|
| Fig. 12. Example of logic cell to implement functions. MAX II EPM2210F324C3 contains 2210 logic elements. |
Part 2: Simulation using a VHDL testbench
Now that we have the circuit synthesised by Quartus Prime in a MAX II device, it must be simulated to obtain its truth table. Generate a testbench template in Quartus Prime. Fig. 13 represents the idea behind a VHDL testbench.
|
|
| Fig. 13. The VHDL testbench concept. |
In a first step, obtain the testbench template. Rename the file from Circuit_W.vht to Circuit_W_tb.vhd and move it to the project location folder.
|
|
| Fig. 14. Obtaining the testbench template. |
In a second step, using the example timing diagram in Fig. 2, translate into VHDL the stimulus signals into a process and set the constant Min_Pulse. This is a VHDL testbench example Circuit_W_tb.vhd from which you can copy only the stimulus process and Min_Pulse constant.
|
|
| Fig. 15. You can edit the testbench schematic in VHDL in two steps. |
Start a project in ModelSim Intel Starter Edition (or in Xilinx ISim or in Active-HDL).
|
Note: remember to change preferred colours in ModelSim when using it for the first time (white background must be used to save ink when printing). |
Project location: C:\CSD\P1\Circuit_W\VHDL\(the same location as above for synthesis)
Project name: Circuit_W_functional_sim
Project library: work_functional
|
|
| Fig. 16. Start a new project for functional (ideal) simulations. Be aware to add the two VHDL files composing the testbench in Fig 13. |
It is time to compile all the project, the two VHDL files: the testbench and the unit under test. You must get green ticks in the status column when zero errors.
|
|
| Fig. 17. Compile all and get ready for starting the simulations. |
Everything is ready now to start running a simulation considering the top entity where the stimulus process for the UUT is written.
|
|
| Fig. 18. Start simulations selecting the testbench top entity in the hierarchy. |
Add signals of interest to the wave diagram using the right mouse button. This operation is like preparing an initial setting of a logic analyser instrument.
|
|
| Fig. 19. Add the signals of interest to the timing diagram. |
Run the simulator for a convenient time (longer than the stimulus duration) and adjust the grid and the time units. Configure your wave diagram so that you do not see the vertical grid lines, as shown in Fig. 20 and get a clearer picture.
|
|
| Fig. 20. Add run command in the console window and adjust the grid and time units. |
Step by step: once you get results correctly, add new stimulus and complete all combinations recompiling the project and restarting the simulations.
|
|
| Fig. 21. Restarting the simulations. |
Run the full simulation process and extract the truth table from the inspection of the logic analyser display (wave window) using time cursors and adding handwritten comments over the pictures after printing, as represented in Fig. 22.
|
|
| Fig. 22. Example of commented waveforms from ModelSim. |
Fig. 23 shows the final truth table result.
|
|
| Fig. 23. Circuit_W truth table and its canonical equations. |
| Specifications | Planning | Developing | 4. Testing | Report | Prototype |
Verification of the truth table. Compare your truth table with results from other methods. For instance, from method II or method IV in Lab1_1 or method III in L1_3. In this way, this section has to say something as simple as
"My Circuit_W generates the same truth table using method III and method II".
| Specifications | Planning | Developing | Testing | 5. Report | Prototype |
Follow this rubric for writing reports.
| Specifications | Planning | Developing | Testing | Report | 6. Prototype |
These are basic ideas consisting of drawing a top schematic to adapt the project to the specific board hardware. Because it is a hierarchical multiple-file design, any circuit based on our design plan C2 can be copied and adapted to be the top entity.We recommend to build this prototype after having completed P3 projects.
DE10-Lite board. This page MAX10 DE10 Lite contains information and the used manual. This is another complete tutorial example introducing and prototyping on the DE10-Lite.
Fig. 24 shows the schematic to adapt the Circuit_W to the FPGA MAX10 populating the DE10-Lite board. All our prototype adaptations will be named in the same way: we will identify the component under design "Circuit_W" and add "_top" suffix.
Prototype location:
C:\CSD\P1\Circuit_W\DE10_Lite\(files)
 |
Fig. 24. Schematic consisting of a top entity with the component and the glue logic to adapt inputs and outputs to the board's hardware. Studying the schematics we see that the switches are connected through a series 120 W resistor to the FPGA pins for protection purposes (pins are also available at expansion connectors).
The two keys, KEY0 and KEY1, are buffered using a SN74LVC2G17 chip and they are active-low including as well an RC debouncing filter. |
  |
|
Using pin planner tool at Quartus Prime navigator we connect signals to FPGA pins. We can export the asignment to a file to keep it save.
|
|
| Fig. 25. Pin planner tool allows assigning circuit signals to FPGA pins. |
This zipped file Circuit_W contains all the required files for implementing project. As shown in Fig. 26 the programmer tool is used to download the configuration file to the FPGA target chip.
|
| Fig. 26. Programmer and circuit running for final checking and verification. |
MAXII Micro kit. This is the board MAXII Micro kit board. Rec.
Fig 27 shows the training board populated with a MAX II chip. Expansion connectors in areas A and B can be soldered so that many more FPGA I/O pins are avaialble for prototyping designs.
Prototype location:
C:\CSD\P1\Circuit_W\MAXII_Micro_kit\(files)
|
|
| Fig. 27. Lab training board populated with MAX II EPM2210F324C3 for experimentation. |
As shown in the top schematic in Fig. 28, for this simple project only the buttons and a single LED will be used.
 |
Fig. 28. Schematic consisting of a top entity with the component and the glue logic to adapt inputs and outputs to the board's hardware.
|
 |
|
This is the zipped project Circuit_W containing all the required files to complete this experiment.
| Home Term 24/25-Q1 Contact Products Electronic devices and companies Software Books Magazines Instruments DEE Library EETAC DEEL |
|
|
| Web activa des de 09/2001, @ F. J. Robert, J. Jordana. Web editat amb Microsoft Expression Web 4. El contingut és un complement als materials d'estudi del curs Circuits i Sistemes Digitals disponibles al campus digital Atenea. Llicència:Reconeixement 4.0 Internacional de Creative Commons |