upc eetac_1 Bachelor's Degree in Telecommunications Systems and in Network Engineering

Digital Circuits and Systems (CSD) 

20-21 Q1


Content and skills

Chapter 1 Chapter 2 Chapter 3
Combinational Circuits Sequential Systems Microcontrollers
VHDL C language
EDA tools for CPLD/FPGA: Synthesis and simulation: Lattice Semi ispLEVER Classic - Diamond / ActiveHDL,  Intel Quartus Prime / ModelSim Starter  or Xilinx ISE-Vivado/ISim EDA tools for microcontrollers: Microchip (PIC18F/16F/Atmega) MPLABX / XC8
P12 - P_Ch3: Peripherals: Timers, A/D, I2C, USART, etc.
P11: Peripherals: LCD display.
P10: FSM style of programming. External Interrupts.
P9: Microcontroller architecture. Digital I/O.
P8 - P_Ch2: CLK generators and dedicated processors.
P7: Counters, data and shift registers.
P6: Finite State machines (FSM).
P5: 1-bit memory cells: latches and flip flops.
P4 - P_Ch1: Arithmetic circuits (2C, integers) and ALU. Propagation time and maximum speed of a circuit.
P3: Arithmetic circuits (radix-2): adders, comparators, etc. Multiple-file structural VHDL design: plan C2.
P2: Standard logic circuits: multiplexers, demultiplexers, decoders, encoders. Single-file VHDL design:plan A, structural; plan B, behavioural.
P1: Logic gates and Boolean algebra. Analysis and design: schematics, truth table, minterms, maxterms, SoP, PoS.
Cross-curricular competences (1) (2) (3) (4) (5)
COVID19       VD

General information

Our main learning goal is that upon completion of the course, you will be able to:

Systematically specify, plan, develop, simulate, report, prototype and verify simple digital circuits and systems, using state-of-the-art digital programmable devices and microcontrollers, CAD/EDA software tools and laboratory equipment, by means of cross-curricular competences and PBL methodology.

This course will be taught in a synchronous hybrid mode: online lectures (Tuesday and Thursday) using Google meet and laboratory sessions at C4-129B (Monday) with one-third of the lab subgroup in the room and the other two-thirds online via meet. Assignments will be submitted at Atenea platform.

- The way to attend CSD is simple: let's study and design a project every week by means of this planning. The course work load is 150 hours or 6 ECTS. This is a short presentation (rec.) of course organisation and syllabus.

-  This is an archive of CSD exams with solutions, problems and questions. The problem collection is based on the idea of reviewing and rewriting exam assignments, laboratory experiments and tutorials. These are video recordings to clarify specific topics, concepts and proceeding when using EDA tools and designing circuits. This is the syllabus of CSD as a book table of content; just a way to show you that we are covering the main topics presented in books on fundamentals of digital circuits and systems.

- You are encouraged to participate actively in class or by email,  post questions and answers in our Atenea blogs and help as much as possible your mates working in cooperation as in a real-world company.

- Most of the course class discussion and assessment will be based on your submitted handwritten projects, sketches and solutions. However, in the final project P_Ch3 you will be required to organise a written report and an oral presentation with your cooperative group, optionally documenting your project using a word processor.

- CSD uses virtual desktop technology (VD) and the application virt-viewer which is installed in our classrooms, laboratory C4-129B  and CBL library. This is the web address where to get a connection and some instructions.


Fig. 1. The concept and technology behind a VD. A fully equipped and tuned workstation to be in use anywhere.

- This is the web page from where you can print documents using EETAC printer - scanner machines.

Optionally you can show and archive your projects and reflections by means of constructing your ePortfolio. This device allows discussion on what you have learnt in this 6 ECTS university course. These materials will be useful for you in other subjects in electronics or even in your final bachelor thesis.

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