Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC

Laboratory

Laboratory 11: peripherals: [P11] LCD, [P12] TMR0 + dedicated processor

Timer. Phase #1: time-base with external CLK phase #2: LCD phase #3 : internal TMR0

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This is the group post lab assignment PLA10_11 to be submitted at Atenea before the due date. Study and execute in your computer this LAB11 and the previous LAB10 tutorials before attempting to solve this post lab assignment.

3.7.2. Examples: Timer

3.7.2.1. Timer (design phase#1)

This lab is for developing & testing a Timer circuit organised as in P8 (datapath & control unit). Timer's datapath is conceived as a RAM variable driven by an external CLK (50 Hz) signal connected to an external interrup (INT0). This external CLK is the time-base of the application defining a time resolution of 20 ms.

1. Specifications (Fixed-time timer. Phase #1: external CLK (INT1) time-base )

Design a fixed-time timer (for instance 18.5 s) as represented in Fig. 1. Dedicated processor (FSM + datapath), external INT

Fig. 1.Symbol.

Interrupt-driven: Trigger signal a pushbutton connected at RB0/INT0.

Interrupt-driven: CLK signal connected to RB1/INT1) to generate a time-base of 20 ms.

Two modes of operation: Retriggerable (RT=1) (see for example classic chip 74LS122/123) and non-retriggerable (RT=0) (see chip 74LS121). RT value by polling the switch at RA4 (level sensitive signal).

Fig. 2. Basic waveform in non-retriggerable mode of operation.

Fig. 3. Basic waveform in retriggerable mode of operation.

Other features: C language, coding in FSM style, dedicated processor approach, PICDEM2+ board. Compiler XC8, Microcontroller PIC18F4520.

2. Planning

Study notes on how such (programmable) timer can be planned as in Chapter II using VHDL and FPGA/CPLD devices. In this way all the concepts involved will be known to you. Review as well P8 assignment on a programmable timer Timer_MMSS that is more complex but with the same organisation. Fig. 4 below shows yet another dedicated processor design. The FSM has to be able to attend trigger active edges to start operation and control the datapath, for instance an up binary counter.

Fig. 4. Example dedicated processor to perform timer function.

A) Planning hardware

Determine where to connect OSC, MCLR_L, Trigger, CLK, Timer_out and RT.

Fig. 5. Hardware connections.

Step 2: Software. Draw the hardware-software diagram.

Fig. 6. Hardware-software diagram.

B) Planning software

A FSM that also will include the datapath in its main loop.

Fig. 7. General computer software organisation. ISR() will determine what is the interrupt source, trigger button or external CLK. Datapath function for counting CLK periods will be unused when IDLE.

Draw the state diagram.

Fig. 8. State diagram for the FSM. The system is either idle or timing. However, peripherals and operating devices will require setting up and stopping extra states to prepare them to work properly.

Program init_system() function, configuring ports and interrupts INT0 and INT1.

	Fig. 9. Data direction registers (TRIS). PORTB pin 1 is INT1, PORTB pin 0 is INT0. PORTB pin3 is Timer_out.

Program state_logic() so that all state transitions in Fig. 8 are implemented. Truth tables and flowcharts.

Fig. 10. State logic and its equivalent behavioural flowchart (below) where C instructions are inferred with no difficulties.

Program output_logic(). Truth tables and flowcharts. As seen in Fig. 6 hardware-software diagram, output logic has to generate Timer_out circuit's output and control signals for managing the datapath counter.

Fig. 11. Output logic. Truth table and flowchart.

Program datapath() as a P7 counter solved now in software.

Fig. 12. Datapath is a counter described using RAM variables. Be aware that executing assembly instructions requires some us, consequently introducing some systematic error if what we have in mind is measuring real-time.

Write ISR() flowchart. so that the computer program can be sensitive to events such CLK rising edge and trigger button falling edges.

Fig. 13. ISR() flowchart.

Program read_inputs(), write_outputs(). Truth tables and flowcharts.

Fig. 14. Read_inputs() captures RT value when executed. This value is saved in a convenient RAM variable var_RT.

Fig. 15. Write_outputs() this time handles only var_Timer_out.

Target chip PIC18F4520. Project location:

C:\CSD\P12\Timer\(files)

3. Developing and 4. Testing the design using EDA tools

A) Developing hardware

The basic timer represented in Fig. 16. Timer.pdsprj hardware.

Fig. 16. Microcontroller connections.

B) Developing software

Source file example Timer.c containing the translation of all planned flowchart .

C) Step-by-step testing

The idea is, as usual, write and run a bit of code with both windows, the hardware Proteus environment and the software IDE running simultaneously for easy debugging. Use watch window and break points to control the program sequence and monitor RAM variables of interest for each function.

Fig. 17. Basic timer running while watching RAM variables.

5. Report

Follow this rubric for writing reports.

6. Prototyping

Use the training boards and perform laboratory measurements to verify how the circuit works.

Modify timing period to 6.5 s. In this application the key point is the timing period precision. Is it 6.4998 s or 6.50001 s? How to measure timing precision? What can be done to improve it?

Lab10

Laboratory

Laboratory 11: peripherals: [P11] LCD, [P12] TMR0 + dedicated processor

Timer. Phase #1: time-base with external CLK phase #2: LCD phase #3 : internal TMR0

Lab AR

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3.7.2.2. Timer_LCD (design phase#2)

Timer enhanced with LCD to show ASCII messages (and numerical data)on the LCD screen.

1. Specifications (Fixed-time timer. Phase #2: LCD peripheral)

Design a fixed-time timer (for instance 18.5 s) adding an LCD screen for representing information.


Fig. 1. The timer symbol and basic waveform in non-retriggerable mode of operation.

Features:

- Same features as in design phase #1 Timer above.

- In a first step #1 information may be simply ASCII messages, in a second step #2, information may include dynamic data such time in seconds while down counting. The symbol is represented in Fig. 1.

2. Planning