Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC

PLA2: Circuit design using single-VHDL file plans A and plan B

NOTE: This post-lab assignment must be solved only after having studied in detail and completed successfully lab session Lab2 in your computer because you will copy and adapt materials from it.

Specifications

Design one of the circuits proposed in the following table with the plan and options indicated by your instructor.

Example of individual assignments

	Project number	Circuit entity	Design plan	Target chip
Student 1	D1.6 10-sensor water tank level meter	Tank_level_meter	plan A, #1	MAX 10
Student 2	D1.3 5-bit ones counter	Ones_Counter_5bit	plan B	Cyclone IV
Student 3	D1.12 5-bit Gray-binary converter	Gray_bin_5bit	plan A, #1	MAX II
Student 4	D1.12 5-bit Bin-Gray converter	Bin_Gray_5bit	plan B	MAX 10
Student 5	D1.6 10-sensor water tank level meter	Tank_level_meter	plan A, #2	Cyclone IV
Student 6	D1.3 5-bit ones counter	Ones_Counter_5bit	plan A, #1	MAX II
...	...	...

Home Term 23/24-Q2 Contact Products Electronic devices and companies Software Books Magazines Instruments DEE Library EETAC DEEL
Web activa des de 09/2001, @ F. J. Robert, J. Jordana. Web editat amb Microsoft Expression Web 4. El contingut és un complement als materials d'estudi del curs Circuits i Sistemes Digitals disponibles al campus digital Atenea. Llicència:Reconeixement 4.0 Internacional de Creative Commons