UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

PLA1_2

Q&A

PLA2: Circuit design using single-VHDL file plans A and plan B

PLA3

Lab2


NOTE: This post-lab assignment must be solved only after having studied in detail and completed successfully lab session Lab2 in your computer because you will copy and adapt materials from it.

Specifications

Design the circuit proposed in the following table using two projects to compare implementation results. One project is plan B, and the other is plan A with the options indicated by your instructor.

Example of group assignments
  Number, entity to design Plan A option Target chip options
Group 1 D1.10 4-bit radix-2 to Johnson code  converter #1 #1
Group 2 D1.10 8-bit Johnson to binary radix-2 converter #1 #2
Group 3 D1.9 4-bit (nibble) shifter operator #1 #3
Group 4 D1.7 2-digit multiplexed 7-segment display #1 #1
Group 5 D1.10 4-bit radix-2 to Johnson code  converter #2 #2
Group 6 D1.10 8-bit Johnson to binary radix-2 converter #2 #3
... ... ... ...