-------------------------------------------------------------------------------- -- UPC - EETAC - EEL - CSD: Digital Circuits and Systems - DIGSYS -------------------------------------------------------------------------------- -- LAB6 example tutorial on prototyping: Light control top -- Target board: DE10-Lite Terasic -- Target PLD: MAX10 10M50DAF484C7 -- Plan C2: FSM and some additional components for: -- Adapting buttons and LED -- Generating CLK signal from board external oscillator -- 7-segment decoding for displaying FSM internal states. -- Reference and schematic at: https://digsys.upc.edu/csd/P06/lab06/lab6.html -------------------------------------------------------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; ENTITY Counter_mod12_top IS Port ( OSC_CLK_in : IN std_logic; CD_L : IN STD_LOGIC; CE, UD_L : IN STD_LOGIC; Sel_CLK : IN STD_LOGIC; HEX4_L : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); LED : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); END Counter_mod12_top; -------------------------------------------------------------------------------- -- The description of the proposed schematic -- ARCHITECTURE schematic_planC2 OF Counter_mod12_top IS COMPONENT Counter_mod12 IS -- This is the counter to test in the board PORT ( UD_L, CE, CD, CLK : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); TC12 : OUT STD_LOGIC ); END COMPONENT; COMPONENT CLK_Generator IS PORT( OSC_CLK_in : IN STD_LOGIC; CD : IN STD_LOGIC; CE : IN STD_LOGIC; CLK_20Hz_SQ : OUT STD_LOGIC; CLK_1Hz_SQ : OUT STD_LOGIC ); end COMPONENT; COMPONENT HEX_7seg_DECODER IS PORT ( X_IN : IN STD_LOGIC_VECTOR(3 DOWNTO 0); BI_L : IN STD_LOGIC; A_L, B_L, C_L, D_L, E_L, F_L, G_L : OUT STD_LOGIC ); end COMPONENT; COMPONENT MUX_2 IS PORT ( Ch0, Ch1 : IN STD_LOGIC; S : IN STD_LOGIC; E : IN STD_LOGIC; Y : OUT STD_LOGIC ); end COMPONENT; -- Signals for connecting components together (the wires) SIGNAL CD, CLK, ClK1, CLK2, TC12 : std_logic; Signal Q : STD_LOGIC_VECTOR(3 downto 0); BEGIN -- Instantiation of components Chip1 : Counter_mod12 -- from component name => to signal or port name PORT MAP ( CLK => CLK, CD => CD, CE => CE, UD_L => UD_L, Q => Q, TC12 => TC12 ); Chip2 : CLK_Generator -- from component name => to signal or port name PORT MAP ( CD => CD, CE => '1', OSC_CLK_in => OSC_CLK_in, CLK_20Hz_SQ => CLK1, CLK_1Hz_SQ => CLK2 ); Chip4 : MUX_2 -- from component name => to signal or port name PORT MAP ( E => '1', S => Sel_CLK, Ch0 => CLK1, Ch1 => CLK2, Y => CLK ); Chip3 : HEX_7seg_decoder -- from component name => to signal or port name PORT MAP ( X_IN => Q, BI_L => '1', A_L => HEX4_L(0), B_L => HEX4_L(1), C_L => HEX4_L(2), D_L => HEX4_L(3), E_L => HEX4_L(4), F_L => HEX4_L(5), G_L => HEX4_L(6) ); -- Buffers and logic to adapt the board hardware CD <= not (CD_L); -- The board has active-low push-buttons HEX4_L(7) <= NOT(TC12); LED(3 downto 0) <= Q; -- All LED not used connected to '0': LED(9 downto 4) <= "000000"; END schematic_planC2;