-------------------------------------------------------------------------------- -- Tutorial P4 on the design of a 8-bit ones counter -- Structural approach. -- UPC - EETAC - CSD -- http://digsys.upc.edu -------------------------------------------------------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; ENTITY ones_counter_8bit IS PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); Y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END ones_counter_8bit; ARCHITECTURE hierarchical_structure OF ones_counter_8bit IS -- Components to be used: COMPONENT Adder_4bit IS -- From P3 tutorial PORT ( A,B : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Cin : IN STD_LOGIC; S : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); Cout : OUT STD_LOGIC; Z : OUT STD_LOGIC -- Z = 0 when S(3..0) and C4 = 0; ); END COMPONENT; COMPONENT ones_counter_4bit IS PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Y : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END COMPONENT; -- Signals, -- The wires to connect the modules: SIGNAL Cout, Zero : STD_LOGIC; SIGNAL Value_1, Value_2 : STD_LOGIC_VECTOR (2 DOWNTO 0); BEGIN -- Instantiation of up to 4 basic 1-bit adders: Chip1 : ones_counter_4bit PORT MAP ( -- from component name => to signal or port name D => D(7 downto 4), Y => Value_1 ); Chip2 : ones_counter_4bit PORT MAP ( -- from component name => to signal or port name D => D(3 downto 0), Y => Value_2 ); Chip3 : Adder_4bit PORT MAP ( -- from component name => to signal or port name A(3) => '0', A(2 downto 0) => Value_1, B(3) => '0', B(2 downto 0) => Value_2, Cin => '0', S => Y, Cout => Cout, Z => Zero ); -- Other circuits and equations: not necessary END hierarchical_structure;