-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:15:09 03/16/2012 -- Design Name: -- Module Name: C:/Users/FJSR/Dropbox/CSD/EX1B/HEX_7SEG_DECODER_SoP/HEX_7SEG_DECODER_tb.vhd -- Project Name: HEX_7SEG_DECODER_project -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: HEX_7SEG_DECODER -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY HEX_7SEG_DECODER_tb IS END HEX_7SEG_DECODER_tb; ARCHITECTURE behavior OF HEX_7SEG_DECODER_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT HEX_7SEG_DECODER PORT( X_IN : IN std_logic_vector(3 downto 0); BI_L : IN std_logic; A_L : OUT std_logic; B_L : OUT std_logic; C_L : OUT std_logic; D_L : OUT std_logic; E_L : OUT std_logic; F_L : OUT std_logic; G_L : OUT std_logic ); END COMPONENT; --Inputs signal X_IN : std_logic_vector(3 downto 0) := (others => '0'); signal BI_L : std_logic := '0'; --Outputs signal A_L : std_logic; signal B_L : std_logic; signal C_L : std_logic; signal D_L : std_logic; signal E_L : std_logic; signal F_L : std_logic; signal G_L : std_logic; -- No clocks detected in port list. Replace below with -- appropriate port name constant Min_Pulse : time := 10 us; BEGIN -- Instantiate the Unit Under Test (UUT) uut: HEX_7SEG_DECODER PORT MAP ( X_IN => X_IN, BI_L => BI_L, A_L => A_L, B_L => B_L, C_L => C_L, D_L => D_L, E_L => E_L, F_L => F_L, G_L => G_L ); -- Stimulus process stim_proc: process begin -- Circuit initialisation period (do nothing). wait for 100 ns; wait for Min_Pulse*10.5; -- Let's start the stimulus activity X_IN <= "0110"; BI_L <= '1'; -- Approximate signal durations to your timing diagram sketch taking -- the "Min_Pulse" variable as the time unit -- Avoid simultaneus signal changes as much as possible. wait for Min_Pulse*5.2; X_IN <= "1011"; wait for Min_Pulse*1.15; BI_L <= '0'; wait for Min_Pulse*2.15; X_IN <= "0010"; wait for Min_Pulse*3.35; BI_L <= '1'; wait for Min_Pulse*2.15; X_IN <= "1000"; wait for Min_Pulse*3.35; BI_L <= '0'; wait for Min_Pulse; BI_L <= '1'; wait for Min_Pulse*3.45; X_IN <= "1111"; wait for Min_Pulse*4.22; X_IN <= "0000"; wait for Min_Pulse*4.22; wait; end process; END;