UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL
Analysis and design tutorials Analysis and design assignments Prototypes Exam 1 Exam 2 Questions and assessment

2425Q1

Problem 1

Analysis method I is based on paper work. This is another asynchronous circuit like the P5 highlighted project. After drawing the circuit and annotating the signals of interest, we can infer the timing diagram below generated in three consecutive steps because every flip-flop can work independently: (1) analyse Chip0, (2) analyse Chip1, be aware that W1_L is CLK2 to drive the next Chip2; and (3) complete the logic T2 to deduce Chip2 outputs. Write the levels of interest W(2..0) using another colour and list the numbers.

Scheamtic

Timing diagram

Analysis method II on Proteus simulation allows you to verify your handwritten sequence W(2..0). This is a printing of the waveforms from the logic analyser instrument adding text, blanking the grid and trimming colours.

 Printing logic analyser waveforms

Additionally, you also can use the method III to (1) capture the circuit in VHDL; (2) synthesise the circuit; and (3) run a testbench.

For calculating the maximum speed of operation fMAX we may consider the internal design of the flip-flops as any other standard FSM, as proposed in our tutorials (JK_FF, T_FF and D_FF). This circuit is asynchronous, and thus CLK signals are chained, duplicating the propagation delay, as in this sketch:

Propagation time

 

Problem 2

Expanding and truncating counters is explained in L7.3 lecture and other tutorials like P7 and Lab 7. In this problem a good idea is to imagine two steps:

(1) Expanding two components Counter_mod16 to generate a Counter_mod256., in this way you have room to accommodate your 21 states (5 bits required).

(2) Truncate the number of states and restrict them to 21; let them be between 11 and 23 using LD control signals to jump from 0 --> 31 and also from 23 --> 11.

Stratetegy for counting

For instance, chaining two Counter_mod16 we can expand the number of states to 256: 1, 0, 255, 254, ..., 1, 0, 255, 254, ...

Expansion

And now, using parallel load (LD) we truncate to a particular number of states. We can use the Chip2 and Chip1 TC16 to detect the number 0 and load 31. We need extra logic to detect the terminal count 23 and to load the number 11. The schematic below is complete and ready for VHDL translation or for capturing it in Proteus.

Full design ready for VHDL translation

In order to test your circuit, it is a good idea to use (1) Proteus to simulate your design using classic CMOS or LS-TTL chips, or (2) VHDL synthesis tools for FPGA and ModelSim. You can even prototype your counter application in a training board.

 

Problem 3 - Problem 4 - Problem 5

The designs are related to circuits: D2.9 - D3.9, water tank controller; D2.3 - D3.3 LED rotator;  D2.2 - D3.2 stepper motor controller. Use your reports and feedback from your PLA to write similar answers following our systematic methodologies.