UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

 

Timer. Phase #3: internal TMR0  as time base

P10 - P11 - P12

Lab 11

TMR0 peripheral

1. Specifications Planning Dev. & test Prototype report

Design phase #3: Design a fixed-time timer (for instance TP = 18.5 s) as represented in Fig. 1 replacing the internal RAM variable acting as a datapath counter by the TMR0 running as a time base TB  4·TOSC = 500 ns. Let us consider the 8 MHz crystal oscillator on the CSD_PICstick.

Symbol
 

Fig. 1. Project entity is the same in phase #2 eliminating the external CLK and replacing it by the internal TMR0.

Common features:

- The same as in project phase #1 Timer and phase #2 Timer_LCD .

- TMR0 peripheral to generate from the TB = 500 ns a square output signal TMR0_wave with a period 2·TTMR0. (the waveform will toggle every TMR0 interrupt time).

- Optional: Add a buzzer that will sound for 2 s at 1 kHz once the timing period has ended.

 

Questions:

- Measure simulator's "real-time" using break points and step mode.

- Watch variables of interest.

- Modify parameters to generate TP =  2.23 s.

- Modify parameters to generate TP =  5.00 s when XTAL OSC is 12 MHz.

- Implement the circuit in the CSD_PICstick as a prototype and perform measurements to characterise the circuit's performance.

Specifications 2. Planning Dev. & test Prototype report

A) Planning hardware

The schematic is simpler from phase #2 because CLK is removed. We can use port pins connected to the CSD_PICstick available resources, as shown in Fig. 2. We have to consider the hardware belonging the the TMR0 peripheral as another project module.

Hardware
TMR0 hardware

Fig. 2.Hardware schematic for the top timer application and also the TMR0 peripheral hardware to configure. 

B) Planning software

Study how the TMR0 works. Hardware configuration bits and registers: CLK edge, CLK source, prescaler selection, TMR0 in 8-bit or 16 bit mode, hardware interrupt on overflow (terminal count) TMR0IF and variable var_TMR0_flag.

The datapath capable of counting real-time is TMR0 peripheral configured as a timer; the control unit is a FSM running in the main loop. Draw the hardware-software diagram as in Fig. 3.

hardware-software

Fig. 3. Hardware-software diagram representing in dotted green lines the circuit that has become the datapath for calculating real-time from an internal time-base derived from system OSC.

Explain the hardware-software diagram of the TMR0 timer.

Design equation using the prescaler (N1), counter TMR0 (N2), and (software) postscaler (N3) when required:

TP = 4 · TB · N1 · N2 · N3 = TTMR0·N3

How to increase counting capacity to any arbitrary large timing period? 

Fig. 4 shows how the state diagram may be adapted to generate timing periods using TMR0.

State diagram

Fig. 4. State diagram for the FSM.

Program init_system() function configuring ports, interrupts and the TMR0.

Symbol

Fig. 5. TRIS registers.

Discuss the state-logic() truth table and flowchart.   

Symbol

Fig. 6. state_logic().

Discuss the output-logic() truth table and flowchart.   

truth table

Fig. 7. Truth table for the output_logic() representing the instructions to the datapath and outputs.

Program ISR() to acknowledge interrupts from TMR0 and INT0 solving as well the datapath operation of real-time counting.

Symbol

Fig. 8. ISR().

Program read_inputs(), write_outputs() as in phase #2 or phase #1.

Project location:

C:\CSD\P12\Timer_LCD_TMR0\(files)

 

Specifications Planning 3. Dev. & 4. test Prototype report

A) Developing hardware

This is the "Timer_LCD_TMR0.pdsprj" hardware including the LCD and the TMR0.

Chip diagram using the TMR0

Fig. 8. The variable var_Timer_flag is derived from the internal TMR0. Therefore, the external pin RB1/INT1 can be used for another purpose.

 

B) Developing software

These LCD library files "lcd.c", "lcd.h" has to be included in the project. The file "config.h" contains all the microcontroller configuration bits. This is the example software source code "Timer_LCD_TMR0.c". Generate the executable (*.hex) and debugging files (*.cof).

 

C) Step-by-step testing

The idea is, as usual, write and run a bit of code with both windows, the hardware Proteus environment and the software IDE running simultaneously for easy debugging. Use the watch window and break points to control the program sequence and monitor RAM variables of interest for each function.

Circuit running and watching variables

Fig. 9. Circuit running and watching variables of interest.

We can measure with the oscilloscope the circuit performance, for instance N3 = 125 generates a TP = 0.5 s, as shown in Fig. 10.

OScilloscope waveforms

Fig. 10. Waveforms printed from the Proteus oscilloscope. Interrupts Zooming the TMR0_wave activated while timing, we can observe how TMR0IF flags are generated every TTMR0 = 4 ms.

 

(update) NOTE: A new feature: Fig. 11 is the same circuit Timer_LCD_TMR0.c to represent dynamic data while counting. Real-time processing is solved in Timing state.

dynamic data

Fig. 11. Displaying "real-time" in one-tenth of a second resolution on the LCD.
circuit

Fig. 12. Picture of the same timer representing and updating time every tenth of a second.

 

Specifications Planning Dev. & Test 5. Prototype Report

Board CSD_PICstick . Target microcontroller: PIC18F46K22. Tools: MPLAB X + XC8 + Proteus + VB8012 compact instrumentation. 

Experiment #1: Run the application and visualise results using the board resources. This is for checking the installation of the tools and programming environment.

 

Experiment #2: Download and program the target chip (*.elf) to use the in-circuit debugger. Watch RAM variables in MPLABX IDE. Add breakpoints and follow the program execution as we did in Proteus.

 

Experiment #3: Drive and visualise digital signals using instruments.

Fig, 13 shows the connections to theVB8012 using the 40-pin header.

Header connections

Connections

Fig. 13. 40-pin header connections to the VB8012.  And yet another schematic symbol indicating signals of interest, header pin numbers and instrument probes in different colours.

 

Picture of the VB8012 connections

Fig. 14. Picture of the experiment (the LCD is not connected).  
Waveforms annotated

Fig. 15. Printing and annotating the captured logic analyser waveforms. Here we are showing a timing period TP = 1.32 s (N3 = 330)

 

Modify the system to add the buzzer to sound the alarm for 2 s when the timing period has finished. 

 


TMR2 can be used instead of TMR0 as proposed in this design phase #4: Timer_LCD_TMR2.

 

Specifications Planning Dev. & Test Prototype 6. Report

Follow this rubric for writing reports.