UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

 

  

Basic concepts on TMR0

L12

How to use an embedded timer driven by an internal time-base?

1. Architecture and configuration bits

Study peripheral timer TMR0  architecture and configuration possibilities rec. If TOCS = 1, it is a counter of external pulses (events); if TOCS = 0, is a timer derived from the internal time-base FOSC/4.

architecture Timer0

Fig 1. Hardware components (a kind of RTL view) of the Timer 0 (TMR0) of the Microchip PIC16F877A. A similar one can be found for any other peripheral timer like TMR1 or TMR2 of the same family, or for similar devices like the Atmel ATmega8535 chip or the PIC18F4520.

 

TMR0 Analysis

Fig 2. Circuit analysed from CSD point of view.

2. Example project (TMR0 as timer): 18.5 s timer driven by an internal timebase based on TMR0

- Timer_LCD_TMR0 (design phase #3 of the tutorial 18.5 s timer in Lab11)

 

3. Example project (TMR0 as counter): Counter of external events

Hardware-software model. Example of a typical application.