UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

 

  

Basic concepts on TMR2 peripheral

L12

A timer with hardware parellel load

1. Architecture and configuration bits

Study peripheral timer TMR2 architecture and configuration possibilities.

  1. Search for the peripheral section in the microcontroller datasheet. 
  2. Analyse the peripheral's schematic or block diagram in Fig. 1. Determine what is its main characteristic compared with TMR0.
  3. Determine its design equation on how to use it in our applications.

http://digsys.upc.edu/ed/CSD/units/Ch4/U4_14/img9.jpg

Fig 1. Hardware components (a kind of RTL view) of the TMR2 of the Microchip PIC16F877A.

 

TMR2 discussion

equation

Fig 2. Interpretation of TMR2 architecture using CSD conventions. Thus, a var_TMR2_flag is generated after a timing period TP.

 

2. Example project: 18.5 s timer driven by an internal TMR2 timebase

- Timer_LCD_TMR2 (design phase #4 of the tutorial 18.5 s in P12)