UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL



Basic concepts on external interrupts


How to detect active signal edges and affect program execution?

1. Polling vs. interrupts

The key concepts of polling inputs in the main program and interrupts to the main program. Polling is cyclical and repetitive because is installed in the main loop, however, it is not a periodic process because the specific timing in which signals are polled depends on the loop execution time, software bifurcations and number of instructions in each path before repeating the loop.


2. External interrupt circuit. Port pin and edge detection concept (hardware flag)

A port pin with INT specialised hardware rec..

port B pin0 Fig. 1. Electronic circuit for PORTB as presented by Micrichip. As a generic PORTx is studied in detail in this unit on input/output configuration.

This time, we pay attention to the bottom section of the schematic related to the specificity of RB0/INT; the pin is an edge sensitive input connected to INTF  edge detector to allow external interrupts.

These are a couple of slides (1) (2) on how an interrrupt circuit may be designed. The concept to detect an active edge (edge detector) may be similar to converting the external CLK signal into enable (E) when studying how to design an RS_FF from an RS latch in P5.

The idea of the Schmitt-trigger comparator/buffer with hysteresis transfer funcion.


3. Interrupt logic to enable and attend interrupts

Fig. 2 shows interrupt logic for a PIC16F because it is a little bit simpler than in a PIC18F. This is the same interrupt schematic for a PIC18F4520 (datasheet chapter 9) that includes interrupt priority. The main idea behind such interrupt logic is to allow enabling/disabling each interrupt source. Configuration bits in some registers allows controlling which device is allowed to interrupt the CPU main program.

Enabling external interrupts. Configuration bits.


Fig. 2. Representation of the PIC16F877A interrupt logic and the way to detect a signal edge event. PIC18F4520 is a little bit more complex with interrupt priority.

And the idea on how an external active edge detected at port B pin 0 can generate interrupt INT is represented in Fig. 2. This port B has s well the possibility to use internal transistors P-MOS acting as pull-up resistors when configured by bit RBPU_L (port B pull-up), in this way we can even save external resistors attached to push-buttons and switches.


4. Interrupt service routine. Software flag

Finally, what we do in CSD once the interrupt is acknowledged is to set a software flag such var_ST_flag, simply another RAM char variable, to be able to assert state diagram transitions. Study several examples in P10, P11 and P12 to analyse this mechanism.

Remark the difference of the interrupt mechanism with respect to the polling/reading mechanism that only happens when the main loop is executing such instructions in read_inputs(), generating a variable polling time of the input level at the speed of loop execution missing signal transistions.


INT mechanism

Fig. 3. This slide explains polling and interrupt mechanisms.

This is an example of falling/rising edge detector based on logic gates.

falling edge

Fig. 4. When EDG = 0, the NXOR gate becomes a NOT gate and the circuit generates tiny pulses on falling edges considering tp propagation delay on the NOT gate C = B'. Example of edge detector in Proteus: the 4049 CMOS inverter has a larger propagation delay than LS-TTL gates, enough time to set the latch.

It is easy associate such edge detector with a latch to generate INTF as shown in Fig. 5.

falling edge interrupt

Fig. 5. Example of interrupt hardware.


Interrupts in RB pins wil be described in unit RB_INT.