-------------------------------------------------------------------------------- -- Example of a complete Timer_MMSS -- The datapath component -- This is the component specialised in digital operations and calculations -- like counting and selecting data -- Strategy: Schematic composed of several operational resources like -- data multiplexers and counters --------------------------------------------------- -- Project P8 - CSD -- http://digsys.upc.edu -------------------------------------------------------------------------------- --------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Datapath IS PORT( CD : IN std_logic; CLK_1Hz_SQ : IN std_logic; --CLK's for the couter CLK_20Hz_SQ : IN std_logic; CLK_1_6kHz_SQ : IN std_logic; --CLK for audio sound CE : IN std_logic; -- to control the Counter_MMSS UD_L : IN std_logic; SEL_CLK : IN std_logic; SEL_sound : IN std_logic; -- Control the sound ON/OFF SEL_sec_LED : IN std_logic; -- Control the Seconds LED DMT, DMU : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); DST, DSU : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); S_LED : OUT std_logic; Soundwave : OUT STD_LOGIC; TCH : OUT std_logic -- this is the status signal ); END Datapath ; ARCHITECTURE schematic OF Datapath IS -- Components COMPONENT Counter_MMSS IS PORT ( UD_L, CE, CD, CLK : IN STD_LOGIC; DMT, DMU : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); DST, DSU : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); TCH : OUT STD_LOGIC ); END COMPONENT; COMPONENT MUX_2 IS PORT ( CH0 :IN STD_LOGIC; CH1 :IN STD_LOGIC; E :IN STD_LOGIC; Y :OUT STD_LOGIC; S :IN STD_LOGIC ); END COMPONENT; -- Signals for connecting components together (just the internal wires) SIGNAL CLK_1 : std_logic; BEGIN -- Instantiation of the components Chip1 : Counter_MMSS PORT MAP ( -- from component name => to signal or port name CLK => CLK_1, CD => CD, CE => CE, -- The general CE UD_L => UD_L, DMT => DMT, DMU => DMU, DST => DST, DSU => DSU, TCH => TCH ); Chip2 : MUX_2 PORT MAP ( -- from component name => to signal or port name CH0 => CLK_1Hz_SQ, CH1 => CLK_20Hz_SQ, E => '1', Y => CLK_1, S => SEL_CLK ); -- The additional logic: Soundwave <= CLK_1_6kHz_SQ and SEL_sound; S_LED <= CLK_1Hz_SQ and SEL_sec_LED; END schematic ;