After studying the content of these projects, you will be able to:

• Explain the meaning and use of signals such CE, LD, TC, Q, Din, etc.

• Design synchronous canonical standard counters using FSM methodology.

• Design any kind of counter selecting one or several of the following strategies:

  • Plan X: as a typical enumerated FSM in P6.

  • Plan Y: as a scalable block based on STD_LOGIC_VECTOR signals.

  • Plan C2: using building blocks like standard counters and other components as in Chapter 1.

• Design data registers that are scalable to n bits.

• Design shift registers that are expandable to n bits.

• Design applications of sequential systems using registers and counters as building blocks.