After studying the content of these projects, you will be able to:

• Implement the basic RS latch using NOR or NAND gates.

• Deduce a data flip-flop (D-FF) from an RS latch.

• Explain the concept of a clear direct (CD) (asynchronous reset) and set direct (SD) (asynchronous set).

• Explain the concept of CLK signal.

• Generate CLK and control input signals in Proteus (Easy HDL) and in VHDL testbenches.

• Describe the specifications of flip-flops (RS_FF, JK_FF, D_FF and T_FF): function table, state diagram, timing diagram and symbol.

• Analyse simple asynchronous circuits based on latches or flip-flops (for instance, the 7493 chip).

• Explain the idea of sampling input values (level-sensitive signals) and synchronicity.

• Explain the concepts of time resolution and glitches/noise in synchronous digital systems.

• Analyse simple synchronous and asynchronous circuits based on flip-flops and latches.

• Debounce and synchronise digital signals from pushbuttons and switches.

• Find characteristics of classic (LS, HCT, etc.) 1-bit memory cell chips.

• Define the CLK to output delay time (tCO).

• Develop projects in VHDL based on RS latches and flip-flops.

• Develop projects in Proteus based on RS latches and flip-flops using classic libraries (CMOS, LS-TTL).

• Explain the VHDL description of a D_FF.

• Run functional and gate-level simulations to test and verify the performance of circuits based on flip-flops and latches.

• Connect a bank of latches or flip-flops to build n-bit memory cells.

• Implement logic functions using the method of ROM memories.

• Explain the initial idea of a finite state machine (FSM) applied on flip-flops.