SP2_1 Q&A	SP2_2: Analysing circuits based on 1-bit memory cells (FF)	SP2_3 Lab5

NOTE: This subproject must be solved only after having completed successfully lab session Lab5 because you will copy and adapt materials from it.

1. Specifications

This lab exercise is similar to the problems proposed in P5. With the aim of comprehending how FF work, let us analyse using three methods the circuit based extracted from chip 74LS93A represented in Fig. 1.

Method 1 (pen and paper). Analyse the circuit in Fig 1 drawing a timing diagram sketch to see how each flip-flop evolves in time. Determine what kind of output codes are generated each CLK cycle. What is the function of this circuit?

Method 2 (Proteus). Capture the circuit in Proteus and run simulations to check whether your analysis is correct. Use the logic analyser instrument to represent both inputs and outputs in function of time. This a Proteus circuit to play with flop-flops as if we were in the laboratory building such circuits for real using classic 4000 CMOS series.

Method 3 (VHDL). Capture the circuit in VHDL as a plan C2 structure (Fig. 1d), synthesise it and run a simulation testbench to represent all inputs and outputs in time in a wave timing diagram. You can use JK_FF or T_FF as components. What is the maximum CLK frequency when picking a target chip MAXII EPM2210F324C3?

Fig. 1. 74LS93A classic commercial chip. a) Datasheet diagram, b) symbol, c) waveforms, d) internal structure adapted to CSD conventions.

 

2. Planning

As usual in CSD, before starting, and also for preparation of cooperative group work, try to organise your project in a mind map. In this way, all the queries and questions will be referring to a given process, method or solution step.

Fig. 2. Mind map including concepts and ideas for planning this analysis project.

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Project locations:

C:\CSD\P_Ch2\SP2_2\Paper\(pictures, scanned docs, datasheets, etc.)

C:\CSD\P_Ch2\SP2_2\Proteus\(Proteus files and examples, pictures, results, etc.)

C:\CSD\P_Ch2\SP2_2\VHDL\(projects, simulations, results, etc.)

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3. Developing

This exercise must be solved only after having completed successfully lab session Lab5 on analysis of circuits using gates and FF. Several other similar additional circuits with solutions are posted at exams page. Be aware that a key issue for this kind of asynchronous circuits is considering the propagation delay. 

Functional simulations are intended for method 3 on VHDL. Gate-level VHDL simulations (or Proteus captures on specific transitions using the logic analyser instrument) will allow the visualisation and measurement of signal transitions in ns range and at the same time realise how complicated or sometimes unpredictable are such asynchronous circuits.

 

4. Testing

As in the SP1_1 analysis projects, add simply a page indicating that the same timing diagram and sequence of binary codes is deduced in all the three methods. You can discuss as well advantages and disadvantages of each analysis method.

 

5. Report

In this tutorial there are proposed three analysis projects for comparing results.

Method 1 (pen & paper) requires sections 1 - 2 - 3 - 4.

Method 2 (Proteus) requires sections 1 - 2 - 3 - 4.

Method 3 (VHDL) requires sections 1 - 2 - 3 - 4 .

Theory and additional content may be included in section 1 on specifications of a given project. Specifications (1) and test (4) sheets are very similar for all the three projects. 

Follow this rubric for writing reports.

 

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Optional. Second circuit for comparison and further discussion

Specifications

Fig. 3 represents a circuit based on D_FF found browsing Internet. Let us name it Circuit_DFF. We have adapted it as usual to our conventions and naming style so that we can use our set of tools to analyse it (Fig. 4). Input Enable is not necessary because it is simply a CLK blocker when '0' preventing the circuit advancing in time (in P7 we will present better methods for halting, stopping or freezing a circuit activity without interfering CLK signal).

Determine how does the circuit work, meaning finding the vector output Q(2..0) using the three methods:

Method 1. Handwritten analysis.

Method 2. Proteus capture and simulation.

Method 3. VHDL synthesis and test. What is the maximum CLK frequency when picking a target chip MAXII EPM2210F324C3?

Fig. 3. Circuit.

Fig. 2. Circuit_DFF to be analysed using our three methods.

 

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