UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Lab4

Laboratory

Laboratory 5: analysis of synchronous and asynchronous circuits

[P5] Method 1: pen & paper analysis

Lab6

[20/4]

Individual post lab assignment PLA5 to be discussed next Lab6. Study and execute this lab tutorial before attempting to solve the post lab assignment.

2.3.7. Analysis of asynchronous and synchronous circuits based on flip-flops and logic

2.3.7.1. Method 1: Handwritten pen-and-paper analysis and discussion.

1. Analysis specifications

Method 1: Analyse the circuit in Fig 1 drawing a timing diagram sketch to see how each flip-flop evolves in time. Determine what kind of output codes are generated each CLK cycle. What is the function of this circuit?

Symbol

Fig. 1. Symbol and schematic of the asynchronous circuit to be analysed. CLK is a rectangular wave of TCLK period. Clear direct (CD) is a single pulse any time the user like to initialise the circuit.

Circuit_async

2. Planning

Step-by-step strategy:

- (1) It is better to start solving a very simple circuit, such as a single T_FF driven by a periodic CLK signal and a CD pulse , as it was proposed in its tutorial T_FF.  Imagine as well that T is not always '1', but that it is switching.

- (2) Now, because you have more than one CLK signal, it is better to imagine what happens when you are connecting only two flip-flops. Solve another circuit consisting of two T_FF.  What signals are sample and when?

- (3) Now, you can try to solve the circuit in Fig. 1.

Planning method 1

Fig. 2. Planning ideas for this handwritten analysis method.

Pictures, notes, scanned materials, theory, etc. can be stored in this project location:

C:\CSD\P5\Circuit_async\paper\(files)

Remember before stanting the analysis to name all the signals of interest, for instant de CLK driving the T_FF:

Redraw the circuit

Fig. 3. Name all the signals of interest.

 

3. Development

Paper work development will follow the step by step strategy organised in the plan.

Because you have several CLK signals, better analyse a simpler circuit with only two T_FF.

This circuit contains four CLK signals. It is asynchronous because rising edges are not going to happen exactly at the same time, thus complicating the analysis.

In this circuit, T inputs are always sampled to be '1', as shown in Fig. 3, and the small tCO is not going to be important.

The circuit is generating 16 different states: 15 --> 14 --> 13--> .... --> 1 --> 0 ---> 15 --> ... It is a down counting sequence  in binary radix-2. Therefore, this is 4-bit down counter running in continuous mode.

Timing diagram

Fig. 4. Example of timing diagram and analysis discussion. The complication of this circuit is related to the several CLK signals CLK, CLK1, CLK2, CLK3 delayed each other TCO, and thus false output codes are generated at signal transitions.

4. Test

Compare results with other analysis methods.

 

5. Reporting

Four sections: 1 + 2 + 3 + 4 for Method 1. At least four sheets of paper. Follow this rubric for writing reports. Another four sections 1 + 2 + 3 + 4 for the method used to test solutions.

 

Lab4

Laboratory

Laboratory 5: Analysis of synchronous and asynchronous circuits

[P5] Method 2: Proteus simulation analysis

Lab6

[20/4]

2.3.7.2. Method 2: Using Proteus

1. Analysis specifications

Method 2: Capture the circuit in Fig 1 in Proteus and run simulations to deduce the timing diagram. Use the logic analyser instrument to represent both inputs and outputs in function of time.

Symbol

Fig. 1. Symbol and schematic of the asynchronous circuit to be analysed. CLK is a rectangular wave of TCLK period. Clear direct (CD) is a single pulse any time the user like to initialise the circuit.

Circuit_async

Examples of Proteus latch and flip-flop simulations:

(1) The basic idea of an RS_latch cell (symbol, function table, timing diagram). Run in Proteus and in VHDL the RS_latch example to comprehend how a 1-bit memory cell works.

(2) The basic idea of an RS_FF (symbol, function table, timing diagram). Run in Proteus the RS_FF example to grasp differences with respect a latch. What is the meaning of sampling the value of the cell control inputs R and S? What is the sampling frequency?

 

2. Planning

Capture the circuit in Proteus using components modeled on the same logic family and technology.

Project location:

C:\CSD\P5\Circuit_async\Proteus\(files).

Proteus planning

Fig. 2. Planning method 2.

 

3. Development

Circuit capture using a similar circuit to copy and adapt.

Draw your Circuit_async.pdsprj and simulate in Proteus. This is a Proteus circuit to play with flop-flops as if we were in the laboratory building such circuits for real using classic 4000 CMOS series. The 4027 is a dual JK_FF chip in CMOS technology, and the 74LS73A is a similar chip in TTL-LS.

NOTE: When picking parts from the library to mount your circuit, do this initialization --> Tool --> Global Annotator --> Total.

Example adaptation Circuit_async.pdsprj for CMOS technology.

Circuit_Capture

Fig. 3. Circuit captured in Proteus.

Run simulations using the logic analyser instrument and print and discuss results.

Downcounting

Fig. 4. Example of circuit captured in Proteus with logic analyser results. 

The circuit is generating 16 different states: 15 --> 14 --> 13 --> .... --> 1 --> 0 ---> 15 --> ... It is a down counting sequence  in binary radix-2. Therefore, this is 4-bit down counter running in continuous mode.

 

4. Test

Compare results with other analysis methods.

 

5. Reporting

Sections (1) + (2) + (3) + (4)   (at least four sheets of paper). Follow this rubric for writing reports.

 

Lab4

Laboratory

Laboratory 5: Analysis of synchronous and asynchronous circuits

Method 3: VHDL synthesis and simulation analysis.

Analysis of the propagation delay CLK to output (tCO) using gate-level simulations

Lab6

[20/4]

2.3.7.3. Method 3: Using VHDL tools (plan C2 circuit)

1. Analysis specifications

Method 3: Capture the circuit in Fig. 1 in VHDL as a plan C2 structure, synthesise it and run a testbench simulation to represent all inputs and outputs in time in a waveform logic diagram. How many states does the circuit have? What is the application of this circuit and the output codes? 

Symbol

Fig. 1. Symbol and schematic of the asynchronous circuit to be analysed. CLK is a rectangular wave of TCLK period. Clear direct (CD) is a single pulse any time the user like to initialise the circuit.

Circuit_async

 

2. Planning

Synthesis and simulation.

VHDL analysis

Fig. 2. Planning the solution using method 3.

Pictures, notes, scanned materials, theory and all VHDL project files can be stored in this project location:

C:\CSD\P5\Circuit_async\VHDL\(files)

Solve the questions in the specifications performing functional simulations and observing results.

Measure the circuit maximum speed using gate-level simulations tool (because of the many CLK's Quartus Prime timing analyser is not convenient in this type of asynchronous circuits).

 

3. Development

Translate the circuit schematic into VHDL (this is simply another plan C2 hierarchical circuit).

Circuit_async

Fig. 3. Circuit fully annotated and ready for translation to VHDL.

Start a synthesis project in Quartus Prime for a given target chip

The internal architecture of the circuit proposed in Fig. 1 has to be fully annotated as in Fig. 3 before developing the VHDL project. This is a plan C2 project consisting of two files.

Write down the VHDL file corresponding the Circuit_async.vhd from the schematic above in Fig. 3. The flip-flop description in VHDL is available in its tutorial T_FF.

Synthesise the project Circuit_Async_prj for a given target chip.

Print the RTL schematic and discuss it.

RTL

Fig. 4. RTL produced by the synthesiser.

Print the technology schematic and discuss it. How many resources are used (logic cells and registers)?

tech

Fig. 5. Technology schematic to be tested using gate-level simulations. In red is represented the CLK path from one T_FF to the next. Note how four D_FF registers are used, one per T_FF.

 

Generate a testbench driving CLK and input signals (in this case the CD pulse). Two processes

Fig. 6 shows the generalised VHDL testbench schematic that we have in mind to run simulations for our sequential systems under test. Remark the significant change replacing Min_Pulse constant by CLK_Period to define from now on time resolution.

Fig. 6. General testbench fixture for sequential systems, including at least two stimulus processes: one for the CLK and another for the remaining input ports.

 

Fig. 7 represents the inputs required in this experiment. A periodic CLK waveform of rectangular shape, for instance with a duty cycle = 25% and a clear direct CD pulse that can be repeated when necessary to initialise again the circuit. Make all the timing relative to the constant CLK_Period, that is the equivalent in Chapter 2 to the Chapter 1 constant Min_Pulse.

CLK and CD signals

Fig. 7. CLK and CD activity to be described in the testbench processes. From this activity the simulator will calculate outputs. Normal operation of the circuit can be inspected for example setting CLK_Period = 4 us. And detailed time measurements on signal transitions can be performed setting CLK_Period = 40 ns when testing the real technology view synthesised circuit for a given target chip (FPGA or CPLD).

This is an example testbench file Circuit_async_tb.vhd where to see how the CLK_Period constant is specified and how signal activity (and the CLK generation) is translated into VHDL processes.

Start a new functional ModelSim simulation.

Run the EDA VHDL tool and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms.

Functional

Fig. 8. Waveforms from functional simulation.

Questions solving and discussion.

This circuit looks like that is acting as a 4-bit binary counter in radix-2.

Start a new ModelSim gate-level simulation using the same testbench.

Run the EDA VHDL tool using the same testbench in order to measure the CLK to output propagation delays (tCO). You can also calculate the maximum frequency of operation. 

all

Fig. 9. Results from a gate-level simulation zooming all the test time to see that it works as expected.

transition

Fig. 10. Results from a gate-level simulation focusing a single transition in ns time resolution window.

4. Test

Compare results with other analysis methods. For instance, Fig. 13, Fig. 6 and Fig. 3 are giving the same outputs: down counting continuously "1111", "1110", ..., "0000", "1111", ...

 

5. Reporting

Follow this rubric for writing reports. Sections (1) + (2) + (3) + (4)   (at least four sheets of paper).

 

 

Extra optional (recommended): enhance the circuit in Fig. 1 as shown in Fig. 11 adding a decoder Dec_4_16 to convert 4-bit radix-2 output codes to 16-bit one-hot codes for better observing how poorly is performing in transitions from one code to the next. The point here is to see the drawbacks of such asynchronous circuits with respect to synchronous designs based on finite state machines (FSM) to be studied in the next P6.

Circuit_async_onehot

Fig. 11. Symbol of the modified circuit with 16-bit one-hot vector output Q(15..0). Only one output must be high at a time.

In this way, it is even easier to visualise the problems at CLK transitions of this circuit. Project location at:

C:\CSD\P5\Circuit_async_onehot/(files)

Circuit_async with onehot outputs

Fig. 12. Schematic of the asynchronous circuit with one-hot outputs designed to observe the poor performance of asynchronous circuits based on CLK rippling or using CLK as another logic signal to control flip-flops.

 

The VHDL description of the decoder component is found in Dec_4_16 tutorial eample page. Thus, the project resulting from the translation of Fig. 12 schematic Circuit_async_onehot.vhd will generate one-hot outputs.

Circuit RTL

Fig. 13. RTL produced by the synthesiser of the project with one-hot outputs.

 

Similar waveforms in the logic analyser can be observed running Counter_onehot_16bit_async using a similar testbench Circuit_async_onehot_tb.vhd. 

Gate-level view

Fig. 14. Results from a gate-level simulation focusing a single transition in the Circuit_async_onehot.

 

Optional. Compare Fig. 14 with gate-level results from a canonical FSM-based synchronous design of a 4-bit binary down counter (glitch, propagation time, etc.).


Books and internet references  

This All About Circuits article (be aware that the naming conventions and procedures are different) is adequate to examine in detail the problem of asynchronous circuits like this one analysed in this lab project based on rippling CLK signals through a series of flip-flops.