Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC

PLA5: Analysing circuits based on 1-bit memory cells (FF)

NOTE: This post lab assignment must be solved only after having completed successfully lab session Lab5 because you will copy and adapt materials from it.

Specifications (Circuit_A)

Fig. 1 represents the internal circuit of chip 74LS290 containing several chained flip-flops and logic gates from its datasheet. Let us adapt it as usual to our naming style and conventions. This PLA is adapted from problem A2.2.

We can use our set of tools to analyse Circuit_A represented in Fig. 2 built using this chip resources and external logic gates.

Fig. 1. 74LS290 chip equivalent internal circuit.

Read its datasheet to determine how does it work (what is the funcion of each pin). Some J and K inputs are not driven, we will assume that they are connected to '1'.

Analyse Circuit_A in Fig. 2 using method 2 or method 3 (your instructor will tell you which). Determine how does the circuit work, meaning finding the vector output P(4..1) in a clocked (CLK) timing diagram.

Method 2. Proteus capture and simulation. Project location:

C:\CSD\P5\PLA5\A\Proteus\(files)

Method 3. VHDL synthesis and test. What is the maximum CLK frequency when picking the PLD target chip indicated by your instructor? Project location:

C:\CSD\P5\PLA5\A\VHDL\(files)

Test your solutions using method 1: handwritten analysis drawing the timing diagram. Project location:

C:\CSD\P5\PLA5\A\paper\(files)

Fig. 2. Circuit_A to be analysed using our three methods.

Specifications (Circuit_B)

We can use our set of tools to analyse Circuit_B represented in Fig. 2 built using this chip resources and external logic gates.

Fig. 1. 74LS290 chip equivalent internal circuit.

Read its datasheet to determine how does it work (what is the funcion of each pin). Some J and K inputs are not driven, we will assume that they are connected to '1'.

Analyse Circuit_B in Fig. 2 using method 2 or method 3 (your instructor will tell you which). Determine how does the circuit work, meaning finding the vector output P(4..1) in a clocked (CLK) timing diagram.

Method 2. Proteus capture and simulation. Project location:

C:\CSD\P5\PLA5\B\Proteus\(files)

Method 3. VHDL synthesis and test. What is the maximum CLK frequency when picking the PLD target chip indicated by your instructor? Project location:

C:\CSD\P5\PLA5\B\VHDL\(files)

Test your solutions using method 1: handwritten analysis.Project location:

C:\CSD\P5\PLA5\B\paper\(files)

Fig. 2. Circuit_B to be analysed using our three methods.

Specifications (Circuit_C)

Fig. 1 represents the internal circuit of chip 74LS92 containing several chained FF from its datasheet. Let us adapt it as usual to our naming style and conventions. This PLA is adapted from problem A2.7.

We can use our set of tools to analyse Circuit_C represented in Fig. 2 built using this chip resources and external logic gates.

Fig. 1. 74LS92 chip equivalent internal circuit.

Read its datasheet to determine how does it work (what is the funcion of each pin). Some J and K inputs are not driven, let us assume that they are connected to '1'.

Analyse Circuit_C in Fig. 2 using method 2 or method 3 (your instructor will tell you which). Determine how does the circuit work, meaning finding the vector output P(4..1) in a clocked (CLK) timing diagram.

Method 2. Proteus capture and simulation. Project location:

C:\CSD\P5\PLA5\C\Proteus\(files)

Method 3. VHDL synthesis and test. What is the maximum CLK frequency when picking the PLD target chip indicated by your instructor? Project location:

C:\CSD\P5\PLA5\C\VHDL\(files)

Test your solutions using method 1: handwritten analysis. Project location:

C:\CSD\P5\PLA5\C\paper\(files)

Fig. 2. Circuit_C to be analysed using our three methods.

Specifications (Circuit_D)

We can use our set of tools to analyse Circuit_D represented in Fig. 2 built using this chip resources and external logic gates.

Fig. 1. 74LS92 chip equivalent internal circuit.

Read its datasheet to determine how does it work (what is the funcion of each pin). Some J and K inputs are not driven, let us assume that they are connected to '1'.

Analyse Circuit_D in Fig. 2 using method 2 or method 3 (your instructor will tell you which). Determine how does the circuit work, meaning finding the vector output P(4..1) in a clocked (CLK) timing diagram.

Method 2. Proteus capture and simulation. Project location:

C:\CSD\P5\PLA5\D\Proteus\(files)

Method 3. VHDL synthesis and test. What is the maximum CLK frequency when picking the PLD target chip indicated by your instructor? Project location:

C:\CSD\P5\PLA5\D\VHDL\(files)

Test your solutions using method 1: handwritten analysis. Project location:

C:\CSD\P5\PLA5\D\paper\(files)

Fig. 2. Circuit_D to be analysed using our three methods.

Example of individual assignments. your instructor will assign you individually a circuit and a method and a chip or technology.


	Circuit	Analysis method	PLD target chip or technology modelled in Proteus
Est. 1	Circuit_A	2	CMOS 4000 library
Est. 2	Circuit_B	3	Cyclone IV
Est. 3	Circuit_C	2	LS-TTL library
Est. 4	Circuit_D	3	MAX II
Est. 5	···	···	···
···	···	···	···

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