
P1 objectives 

After studying the content of these projects, you will be able to:
Use and explain the functionality of logic gates AND, NAND, OR, NOR, XOR, NXOR and NOT.
Find datasheets of small and medium scale of integration (SSI and MSI) integrated circuits.
Analyse a logic circuit built using logic gates (deduce its truth table).
Explain and relate the following concepts to design logic circuits: truth table, canonical algebraic equations: minterms and maxterms, Boolean algebra and logic functions, minimisation: SoP (sum of products) and PoS (product of sums).
Simplify or minimise logic functions using software like Minilog.exe.
Use the application WolframAlpha to verify logic equations and determine the truth table of a combinational circuit.
Capture and simulate a schematic using the virtual laboratory software ProteusISIS.
Search books and the internet to find information on the basics of VHDL language and explain the differences between VHDL design styles: structural and behavioural.
Use the register transfer level (RTL) and technology schematic views to inspect the results of the synthesis process.
Explain the basic technological details of an sPLD (22V10), CPLD or FPGA and how to program them to implement logic functions.
Install computeraided design (CAD) and electronic design automation (EDA) tools (Lattice Semiconductor ispLEVER Classic or Diamond, Intel Quartus II or Prime, and Xilinx ISE or Vivado), and run its design flow to implement VHDL projects for sPLD/CPLD/FPGA chips. Essentially the process involves VHDL source files, synthesis, functional simulation, pin assignment, gatelevel simulation, target device programming and prototype verification.
Simulate a logic circuit using EDA tools: ActiveHDL Lattice edition, ModelSim Intel edition or Xilinx ISim.
Use sPLD/CPLD/FPGA development boards to prototype and verify the course projects.