-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:53:56 10/29/2016 -- Design Name: -- Module Name: L:/CSD/1617Q1/P6/Flashing_Lamp/Flashing_Lamp_tb.vhd -- Project Name: Flashing_Lamp_prj -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Flashing_Lamp -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY Flashing_Lamp_tb IS END Flashing_Lamp_tb; ARCHITECTURE behavior OF Flashing_Lamp_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Flashing_Lamp PORT( CLK : IN std_logic; CD : IN std_logic; CLK_5Hz_SQ : IN std_logic; ON_B : IN std_logic; Z : OUT std_logic ); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal CD : std_logic := '0'; signal CLK_5Hz_SQ : std_logic := '0'; signal ON_B : std_logic := '0'; --Outputs signal Z : std_logic; -- Clock period definitions constant CLK_period : time := 1 ms; constant CLK_5Hz_SQ_period : time := 200 ms; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Flashing_Lamp PORT MAP ( CLK => CLK, CD => CD, CLK_5Hz_SQ => CLK_5Hz_SQ, ON_B => ON_B, Z => Z ); -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; CLK_5Hz_SQ_process :process begin CLK_5Hz_SQ <= '0'; wait for CLK_5Hz_SQ_period/2; CLK_5Hz_SQ <= '1'; wait for CLK_5Hz_SQ_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for CLK_period*10; CD <= '0'; ON_B <= '0'; wait for CLK_period*6.12; CD <= '1'; -- reset pulse wait for CLK_period*2.33; CD <= '0'; wait for CLK_period*4.33; ON_B <= '1'; -- let's turn ON the light wait for CLK_period*1.12; ON_B <= '0'; wait for CLK_period*100.12; ON_B <= '1'; -- let's flash the light wait for CLK_period*26.12; ON_B <= '0'; wait for CLK_5Hz_SQ_period*6.12; ON_B <= '1'; -- let's turn OFF the light wait for CLK_period*36.12; ON_B <= '0'; wait for CLK_period*1.12; -- insert stimulus here wait; end process; END;