Guidelines for writing reports and correcting CSD projects	Planning

The aim of writing technical reports is for you to learn to generate quality materials. You can use them to explain your circuits to other students or instructors. Your written reports should be similar to tutorials or highlighted projects used in classes and labs.

CSD reports for postlab assignments submissions are corrected and assessed accordingly to these general ideas:

• Start writing your report only when your project works correctly and you already got some results.

• VHDL reports in Chapters 1 and 2 have at least four sheets of paper, each one representing a project section: (1) specifications - (2) planning - (3) development - (4) verification.

• C language reports in Chapter 3 have at least three sheets of paper, each one representing a project section: (1) specifications - (2) planning - (3 - 4) interactive development and testing (debugging).

• Circuit analysis projects: each analysis method (I, II, III and IV) in P1 section A and in P5 is a report. For instance, analysing a logic circuit using Proteus (method II) requires (1) specifications - (2) planning what you are going to do when using Proteus - (3) development: capturing the circuit using the given library of components and running the simulation to obtain the circuit's truth table - (4) verification: a text paragraph explaining that you have got the same result (truth table) running at least another analysis method, for instance method III.

• Circuit design projects: each plan (A, B, C1, C2, X, Y) is a report. For instance, inventing a combinational circuit using plan A requires the four sections: (1) specifications: truth table, symbol, timing diagram; (2) planning: what equation strategy are you using; (3) development: using EDA tools to synthesise your circuit in a target chip; (4) verification: using VHDL simulation testbenches to check that the circuit generates the specified truth table. 

• Theory and other learning materials are attached to section (1). If you are given several project assignments, include theory only in one project report.

• When using plan C2, the report sections (1) - (2) - (3) - (4) are referring to the main (top) project in design. Other designed components or collateral tutorial work or related theory can be added to the report as annexes. 

Note: If your PLA consist of several design steps and phases: report only step #1 as a full project including all the project sections. Report the next steps as annexes including and describing only what is modified, added or adapted.

• Sketches, schematics, diagrams are handwritten and original. Draw and adapt our materials from digsys, other webs or from books.

• Word processors are NOT used in CSD, use handwritten text instead. For this introductory course on digital design word processors are simply a waste of study time. You can handwrite using both: pen and paper or electronic ink (tablets).

• Academic integrity at the UPC is always considered. Two o more students cannot have the same pictures or materials because each one generates their own classnotes. Group work is always encouraged for discussion purposes and clarifying ideas; all CSD post-lab assignments, exceptuating PLA1 are solved in cooperative groups. 

• Printed results from EDA tools are discussed using pens and handwritten explanations in paper or electronic ink in tablets. A printed schematic or printed computer results without annotations has no value and is not marked.

• Printed graphics have white background and a preferred colour scheme. Do not waste your printer ink printing black backgrounds.

• Sections of VHDL and C language source files are printed following these indications.

• Entity names are not invented. All our project specifications will include the entity names under analysis or design.

• In CSD, projects must be developed and stored in the given locations indicated in the corresponding planning section (2). Other project locations cannot be corrected and will not mark. For instance, the location of the analysis of Circuit_L in PLA1 using Proteus is: 

 C:\CSD\P1\Circuit_L\proteus\(files, pictures, sketches, pdf, etc.)

• VHDL translations and C language source files contain comments and references to the schematics or flowcharts being translated. Or, if we put it in another way: VHDL and C code do not exist without the original schematic/flowchart in paper.

• In testbenches there is no need to print all stimulus vectors or the raw template, print using the colour scheme only a few of them and discuss the waveforms.

• Pay attention and discuss your RTL and technology schematics verifying that they are similar to your planned circuits.

• Never use black background in pictures captured or printed from instruments, it is a waste of ink. You have to change the colour scheme and select a white background.

 

IMPORTANT NOTE: CSD materials and proceedings are specially crafted for you to be asking questions very often. If you have doubts or queries on how to solve or do something, do not hesitate and ask us questions preferably in class or by other ways in order to save much of your study time.

IMPORTANT NOTE: The best way to save and optimise your study time is to attend all lectures and laboratory sessions and be active asking as many questions as possible while taking quality class-notes in paper or electronic ink.

 

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