UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL


P3: arithmetic circuits in radix-2: add, adder, comparator etc. and VHDL hierarchical multiple-file design (plan C2)


 Resources in lectures and labs: L3.1, Lab2 Lab3, L3.2

Example project: Designing an 8-bit binary adder  (type 74HCT283)

1. Specifications

Using VHDL design plan C2, invent an 8-bit binary adder (Adder_8bit) based on simpler chips of the same kind like 4-bit (Adder_4bit) and 1-bit (Adder_1bit) adders. Synthesise it for a target CPLD/FPGA device and test it using VHDL EDA tools. Circuit symbol is represented in Fig. 1 along with its truth table and a sketch of timing diagram.


Fig. 1. a) Symbol of an 8-bit binary adder Adder_8bit (Visio).

This is a project Adder_8bit in Proteus. Run it, code several input vectors and visualise output results. 

Truth table
b) Adder_8bit truth table example values.
Timing diagram

c) Timing diagram sketch showing how the Adder_8bit performs several 8-bit additions. It is ready for translation as a VHDL testbench stimulus process.


Other hierarchical multiple-file VHDL projects (plan C2): Adder_4bit ripple carry,  Adder_4bit carry lookahead, MUX_8, Ones_counter_4bit, Ones_counter_8bit, Enc_4_10, Adder_1bit to get some practice with MoM and MoD,  Comp_1bit using the MoM, Comp_10bit, Comp_4bit planning, rec. on an Adder_2bit.

Other arithmetic circuits using a flat single-file project (plan A or plan B): Comp_1bit using plan A, Comp_1bit using plan B,  Adder_1bit using plan A, Adder_1bit plan B.


2. Planning circuits using hierarchical multiple-component structure

Plan C2 design flow in L3.1.

Even though, as in previous projects we have two possibilities, structural and behavioural, let us design this P3 structurally and hierarchically using COMPONENTS and SIGNALS accordingly to the Plan C2; therefore as a multiple VHDL file project. Learning how to use components is the key point of the CSD course because it'll allow you to plan very large and complicated circuits hierarchically, as you see in Proteus schematics, where you can go "Cntl+C" to the child sheet of each entity subcircuit. Thus, from now on, subcircuits will become components and wires and cables signals.

In order to learn how to translate a project based on plan C2 to VHDL, better if we start with one of Lab3 example projects.   

Because this design is complex, better if we go step by step bottom-up starting from the most simple component: 1-bit full adder (Adder_1bit) at the same time that we practice plan C2. Therefore, this is the proposed general organisation to reach our chip Adder_8bit:

[Project A or Project B] ----> [Project C or Project D]----> [Project E]

Project Adder_1bit:

Project A: Let's design Adder_1bit using the method of multiplexers (MoM). Plan. How many VHDL files are required? Name them all.



Project B: Let's design Adder_1bit using the method of decoders (MoD). Plan. How many VHDL files are required? Name them all. You can use this method of implementing truth tables to design any kind of combinational circuit.



Project Adder_4bit:

Project C: This is a ripple carry Adder_4bit



Project D: This is a carry-lookahead Adder_4bit. So, both the ripple carry and the carry-lookahead adders have the same entity definition but different internal architectures. And so, they will have different performance when implemented in a CPLD chip. This design is similar to the standard chip type 74HCT283.



Project Adder_8bit:

Project E: Design a 8-bit adder using a hierarchy of components. For instance, as represented in Fig. 2.


Fig. 2. Planning the circuit using several components of the same kind. 


Organise the work in cooperative groups to be able to handle this set of projects. 


3. Development

Indeed here you develop up to three projects: PA or PB, PC or PD and PE in the usual way, translating planning schematics into VHDL. One project at a time. Indeed, you can use always this Adder_4bit.vhd (or any other plan C2 circuit like this MUX_8.vhd) to adapt any hierarchical project from now on. Run the EDA tool to synthesise the circuit for a given CPLD or FPGA chip. Print and comment the RTL and technology schematics.

1. Adder_1bit. Write the project files and run projects PA or PB. Print the RTL and also the technology view. Discuss, comment and annotate the schematics identifying components.


Only when the PA or PB are tested (validating its internal design) you can continue with:

2. Adder_4bit. Write the project files and run the projects PC or PD: Print the RTL and also the technology view. Discuss, comment and annotate the schematics identifying components.


Only when the PC or PD are fully tested you can continue in this way:

3. Adder_8bit. Write the project files and run the project PE, Print the RTL and also the technology view. Discuss, comment and annotate the schematics identifying components.

- These files can be used to solve the project PE: Adder_8bit.vhd


Fig. 3. Example of RTL diagram schematic interpreted by the EDA synthesis tool. 


Fig. 4. Example of technology implementation in an FPGA fabric. 


4. Testing

We have to test and verify the projects sequentially in the usual way: using the EDA simulator and a VHDL-based testbench fixture. One project (building block or component) at a time. This is a sequence: One you have tested PA / PB, you can plan-develop and test PC / PD, and so on. The reason is because PA or PB are going to be used as components in the design of PC or PD, so they must be verified before using them in other projects. That is the idea of COMPONENT as a reusable library chip.

 The testbench fixture containing the main ideas cand concepts involved in this schematic is represented in Fig. 5.

testbench fixture
Fig. 5. Testbench VHDL schematic.

To convert the initial timing diagram sketch into a VHDL testbench (for instance Adder_8bit_tb.vhd) write inputs activity starting with a few vectors and the Min_Pulse constant in the template produced by the EDA tool. It's a good idea to adapt test vectors from Adder_4bit to obtain a file like this: Adder_8bit_tb.vhd.

Run the EDA VHDL simulator and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms.

Fig. 6. Analising results from functional simulation of the Adder_8bit.


5. Report

It is required a handwritten original project report containing sections 1 - 2 - 3 - 4, scanned figures with annotations, file listings, diagrams, sketches or any other resources. Theory stuff to comprehend how the circuit works may be included in section 1 on specifications. 

The idea of a report at this level has to be clear for you now: a technical document that demonstrates the way you have designed a given product. Furthermore, it allows you to prepare an oral presentation because it includes everything to generate high quality slides. Simple class notes and conventional exercises may be right for passing exams, but using your project reports you'll be able to teach your peers as if you had become a class instructor.


6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit being designed works for real.

Example 1] A simple initial example from P1: Circuit_W. These are basic ideas consisting of drawing a top schematic to adapt the project to the specific board hardware. Because it is a hierarchical multiple-file design, any circuit based on plan C2 can be copied and adapted to be the top entity. The project Circuit_W for MAXII Micro kit board Rec.


Fig. 7. Schematic consisting of a top entity with the component and the glue logic to adapt inputs and outputs to the board's hardware.


This is the same project Circuit_W tailored for MAX10 DE10 Lite board.

Example 2] Prototyping Adder_8bit circuit into a Terasic Terasic -DE2-115.



Fig. 8. DE0-115 board representing only simple digital inputs (buttons and switches) and outputs (LED and 7-segments).