﻿ Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC - UPC
 Bachelor's Degree in Telecommunications Systems and in Network Engineering

Content

## Project P1 on simple circuits using logic gates

P2

Analysis and design, truth tables, circuits, logic gates, equations, etc.

1.Specifications (What do I have to do?)

Objective 1: analysis. Deduce the truth table of circuits in Fig. 1 following the methods stated in this project's concept map (Visio). Firstly, solve Circuit_C. Secondly, solve Circuit_K to reach a deeper comprehension.
 C = f1(D1, D0, A, B)                                    K = f2(D1, D0, A, B) Fig. 1. Example Circuit_C and Circuit_K to analyse.
 Fig. 2. Generalised symbol for a combinational circuit consisting of n inputs and m outputs.

Objective 2: design. Using Circuit_C truth table as specifications (and secondly the truth table from Circuit_K), invent circuits using gates (plan A) that comply with the truth table found above, for instance:

Circuit_1 - Using canonical equations (C = maxterms ; K = minterns).

Circuit_2 - Using canonical equations (C = minterms ; K = maxterms).

Circuit_3 - Using the minimised equations from minilog.exe (a Karnaugh map computer application) C = SoP (Sum of Products) ; K = PoS (Product of Sums)

Circuit_4 - Using the minimised equations from minilog.exe C = PoS (Product of Sums) ; K = SoP (Sum of Products)

Circuit_5 - Transform the Circuit_3 and build another version (using  C = only NAND gates ;  K = only NOR gates.

Circuit_6 - Transform the Circuit_4 and build another version (using C = only NOR gates ;  K = only NAND gates.

Circuit_10 - Transform the Circuit_5 and build another version using only 2-input NAND.

Note. In this way, you can identify circuits in Fig. 1 as structures derived from other logic equations.

Note. Plan B in P2 generates other circuits from the truth table using VHDL synthesis tools.Plan C2 in P3 generates other circuits using hierarchical structures.

Learning materials

Logic gates

Section A: circuit analysis

• Idea of circuit analysis, for example applied to Circuit_W . This is Circuit_W solution using the proposed analysis method III on Boolean algebra .

• Analysis of Circuit_C using method III. Notes and

• Analysis of Circuit_K using method III. Notes and

• LAB#1 on solving a circuit using the method I. Capture the circuit in Proteus ISIS virtual laboratory and simulate In this unit there is a Proteus tutorial and example circuits.

• LAB#1 on solving a circuit using the method II. Translate the circuit's equation to WolframAlpha and compute to obtain results In this unit there is a WolframAlpha tutorial.

• LAB#2: Tutorial on solving a simple circuit using the method IV Translate the circuit into VHDL, sinthesise and simulate. VHDL EDA tools for all the projects from P2 to P8.

Section B: circuit design:

• Circuit C truth table using maxterms (Circuits 1) and minterms (Circuits 2) rec.

• To design simpler structures use EDA tools like:

- Minilog.exe application to minimise truth tables (tutorial). Circuit C truth table using SoP (Circuits 3) and PoS (Circuits 4)  rec.

- VHDL EDA tools.

• Tutorial: Analysis of a circuit and design of an equivalent one based on canonical expressions. The Wikipedia entry for canonical forms.

• Tutorial: Analysis of a circuit and design of an equivalent one based on SoP or PoS.

• Designing a circuit using any kind of logic equations.

• Some notes on how to design circuits using only NAND or only NOR gates. This is the trick to use only NOR2 or NAND2.

2. Planning (How to solve it?)

Planning means organising and discussing how to proceed to reach solutions. A flow chart of sequential operations will be convenient to explain what to do, how to do it and when.

Section A: methods for analysing a circuit (Visio):  Let's do the same exercise (this is obtaining the circuit's truth table) using four different approaches and compare solutions.  Remember that the truth table must be verified (with other students, with different tools, etc.) before to proceed with Section B.

Place each exercise in a different folder and name them accordingly. Normaly we use as a hard disk drive our network SMB <drive> =  L:\ (available through the repositori de fitxers at the virtual desktop computer). For instance:

<drive>:\CSD\P1\Proteus\Circuit_C.pdsprj (the circuit captured in Proteus to  be simulated)

<drive>:\CSD\P1\Wolfram\Circuit_C.txt  (logic equations compatible with WolframAlpha engine)

<drive>:\CSD\P1\Algebra\circuit_C.jpg, circuit_C.pdf, etc. (pictures, scanned sheets of paper, ...)

<drive>:\CSD\P1\VHDL\Circuit_C.vhd, Circuit_C_tb.vhd  (the VHDL files for running the EDA tools)

Furthermore, something very important: do not start a project or a simulation from scratch but copying and adapting a similar exercise or file from this web. Our web contains many examples and exercises that can be used as templates ready to copy and adapt.

Section B: plans for designing circuits (visio): Once you have the truth table, you can invent/create/infer and test/check/verify several circuits from the specifications.

3. Development (Let's follow the plan to obtain results)

Developing means doing it, executing a given plan to achieve a solution.

Analysis:   The way to proceed and the necessary CAD/EDA tools will depend on the path you follow. For example:

Method I.- Circuit simulator: Draw/capture  the circuit schematic in Proteus and run a simulation. Try all the possible input combinations to complete the truth table.

Method II.- Numerical engine: Write the circuit equations in a text file. Copy and paste them in WolframAlpha and run the engine to obtain the circuit's truth tables or schematics (remember that they have to be interpreted correctly because the inputs variables may be disordered). For example, this is the Circuit_K_equation.txt with some WolframAlpha expressions.

 Fig. 3. Circuit and equation.

Method III.- Analytical method using Boole's Algebra. Pen and paper and discussion in class or in cooperative groups.

Method IV.- VHDL project: Write a VHDL file like this Circuit_K.vhd consisting of entity and architecture based on algebraic equations. Start a VHDL synthesis project using an EDA tool and a VHDL simulation project using a testbench to obtain the circuit's truth table.

Design: The way to invent several circuits derived form the same initial truth table will require different tools and techniques. Thus apply them conveniently to obtain results: canonical equations (sum of minterms or product of maxterms) which are the exact representation of the truth tables, minilog (or logic friday) application to obtain minimised equations (SoP, PoS), only-NOR transformation, only-NAND transformation, etc.

4. Testing (Let's see if the results are correct)

Testing means to check or verify that the solution is correct and agrees with the initial specifications.

Analysis: The best way to check the truth table is by comparison with the truth table obtained by other methods.  Another way is comparing solutions with your team mates.

For example, look at this example of solving the Circuit_K by the method #4 (VHDL synthesis and simulation): Write the circuit equations, translated them to a VHDL file, run the synthesis process, run the simulation of a VHDL test bench, get the truth table interpreting the output timing diagram from the simulator. Compare the truth table solution with others methods. This is an example Circuit_K_tb.vhd file. Fig. 4 shows how to fill in the truth table inspecting the timing diagram once all the combinations are simulated.

 Fig. 4. Example of a simulation using VHDL tools of the Circuit_K (method IV). Testing all the combinations means obtaining the truth table of the circuit as it was done using the method I in  Proteus.

Design: If you have developed a circuit, such as Circuit_3 based on SoP from the initial truth table, a valid way  to test it is by using any analysis method to deduce its truth table.

5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources.

This is a complete example report docx pdf for the Circuit_K solved using the method IV.

6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works. We'll explain this final design step in P3.

Other similar projects

From this initial project where from the same initial truth table you have designed easily more than ten circuit variations based on structural equations,  it is easy to infer that everything can be applied now to any other specification. For instance, can you design a circuit based on only NAND2 gates to count in binary the number of ones driving its four inputs?

Other materials of interest

- Suggested problems on basic Boole's Algebra and logic gates: Problems P1.5. Problems P1.1, P1.2, P1.3. Print them form our draft collection. Work preferably in group and annotate your questions for the next session discussion in class, lab time or in office.

- Q & A. Typical questions related to this P1 project.

- You can read books on the subject or browse the Internet searching the basic theory on digital electronics. For instance, here there is a series of 14 introductory videos to our subject (Dunn, K., Bluegrass Community and Technical College). Some of the videos also include "pdf" notes and exercises and additional web references.

- Another set of online tutorials on electronics. You can use them to clarify concepts or go for a deeper comprehension of many topics covered in CSD (and in other subjects as well).