upc eetac_1 Bachelor's Degree in Telecommunications Systems and in Network Engineering

Project P1/P2 tutorial: EDA tools for synthesis and VHDL simulation

P1 - P2


Intel     Xilinx        Lattice Semiconductor

1. EDA tools 

Synthesise and simulate simple circuits using professional VHDL electronic design automation (EDA) tools from different vendors. This is the VHDL design flow that includes project management, VHDL source files editing, circuit synthesis and simulation, and chip programmming. Other tools such as timing anaysis are also available.  

  • The circuit synthesisers are included and integrated in the project environment.

  • The VHDL simulators are included and integrated in the project environment.

Some commonly used CPLD/FPGA chips in CSD:

  

  • INTEL-ALTERA: Quartus II + ModelSim for a target FPGA chip like the Cyclone IV EP4CE115F29C7N. This programmable chip is placed in the DE2-115 board from Terasic.

  

 

In CSD edit VHDL and C text source files using the Notepath++ enriched text editor (it also contains an spelling checker plug-in). Another similar product that can suit you very well is  the Scriptum text editor, a very convenient free tool for writing VHDL files from the company HDL Works.

 


Intel Quartus Prime Lite + ModelSim Intel Starter Edition

Installation

The Intel Quartus Prime Lite software is installed and available at the EETAC laboratories and computers.

Prime environment

Fig. 1. Quartus Prime project navigator.

However you can register using your UPC email address and download your own copy of these tools for designing hardware from the vendor webs. Install in your own computer the latest version of Quartus Prime Lite.

Quartus Prime Lite

Fig. 2. Quartus Prime download center. The last release by September 2019 was v19.1.

Select the combined file in tar zipped format, unzip it, run the setup and select the items below:

Items to install
Fig. 3. Items to install. Basically, the Quartus Prime Lite Edition, the ModelSim - Intel Starter Edition and the devices Cyclone IV, MAX II and MAX10.

The full package is about 11 GB once installed.

 

 A simple example to synthesise

This is a sample design Dec_4_8.vhd from this tutorial in P2 to run the synthesis process and watch the synthesised schematics and check that everything is all right.

RTL

Fig. 4. Example RTL view.

This is one of the many documents, courses and everything available for learning at Intel web.

VHDL simulation using a testbench fixture

The Intel ModelSim Starter software is installed and available at the EETAC laboratories and computers. It is very similar to the ModelSim PE Student Edition but already trimmed for Intel devices. When installing the Quartus Prime, this simulator is also included in the bundle and installs automatically.  

This is a colour scheme to get a white background.

ModelSim Intel

Fig. 2. The ModelSim Intel Starter Edition simulator.

This is a tectbench fixture to verify that our circuits run correctly.

 

Fig. 3.

 

 

Other similar tutorial exercises

 Gate-level simulation  

Other materials of interest