upc eetac_1 Bachelor's Degree in Telecommunications Systems and in Network Engineering


Project P2 on standard logic circuits: multiplexer, decoder, etc.


MUX_8 (type 74HCT151)

Single-file VHDL (flat) design (Plan A or B)

1. Specifications

Design a MUX_8 in a programmable logic device (PLD) target chip with specifications similar to a classic 74HCT151 chip, following our plans A and B, and using our VHDL design flow and EDA tools for developing and testing.

The chip's logic family (technology), whichever it is TTL, LS, S, CMOS, AS, HC, HCT, F, etc. is not important because the circuit  wil be targeted for a PLD from Intel, Xilinx or Lattice Semiconductor. Thus, only the chip's functionality is considered.


Fig. 1. Package and pin enumeration of classic 74HCT151 chip.

We have to interpret and rename the pins because every company has its own way to name inputs/outputs and organise their product datasheet (Nexperia, Toshiba/Renesas, ON semiconductor, etc.); thus, in CSD we have decided to use our own naming style and rewrite the truth table accordingly. For instance, the pin 12 will be always our input Ch7, an so the same with all the other pins. 

Examine Texas Instruments 74HCT151 datasheet and represent symbol and truth table, renaming inputs and outputs as shown in Fig. 2.


Fig. 2. Symbol adapted from datasheets. A multiplexer is a data selector. 

In Fig. 3 is represented the circuit's truth table.

truth table

Fig. 3. Truth table. Twelve inputs means 4096 binary combinations.

Finally in Fig. 4 there is an sketch of a timing diagram.

timing diagram

Fig. 4. Example of a timing diagram sketch  timing diagram to demonstrate how the circuit works for different inputs and so, be able to translate it later to VHDL as a testbench.

Find and study similar products, like MUX_16, MUX_4, MUX_2 and also demultiplexers.

Learning materials:

- LAB#2. Tutorial on the analysis method IV of a simple circuit using VHDL EDA tools (rec.)

This is the general panorama (pdf, Visio), rec.,  a concept map representing the important terms and definitions to design any kind of circuit in CSD. For a flat design using plan A or B the design flow includes a single VHDL file to define the entity's architecture.

Discussing multiplexers, ideas and specifications.

- LAB#3. Solving the MUX_8 using the plans A (rec.) and B (rec.), which is practically all this project P2.

- This is a similar project to design a Dual_MUX4: the functionality of the classic chip 74LS153 multiplexer.

Discussing binary decoder, specifications  rec.

- Tutorial (Plan A) of a Dec_3_8.

- Tutorial (Plan B) of a Dec_3_8.

Ideas on standard logic circuits: demultiplexers, encoders, etc.


- Tutorial (plan A) HEX to 7 SEG decoder (type 74LS47). Using a structural approach based on minimised equations (SoP / PoS).

- Tutorial (plan B) HEX to 7 SEG decoder (type 74LS47). Using a behavioural (high-level) description (truth table or algorithm) approach.

- The concept of incomplete logic functions (truth table outputs with don't care terms).


2. Planning

This flowchart (Visio) explains the main concepts involved in VHDL design flow process using a single VHDL file (plans A and B).

Accordingly to the way we have discussed chip's specifications, in order to implement the MUX_8 in a single-VHDL file project, let's follow three alternative plans using VHDL tools:


Plan A: structural  

1.- Use a VHDL description of a minimised SoP or PoS logic equations. (Why the canonical maxterms or minterms are not recommended in this plan?). Find equations SoP or PoS running minilog.


Fig. 5. Plan A proposed schematic. Click to see equation PoS to be translated into VHDL in the next section.

2.- Project location. Save the project here:                                         


3.- Find a similar VHDL circuit with an architecture that uses logic equations to copy and adapt.

4.- Write down the VHDL file MUX_8.vhd which contains an architecture of the circuit based on equations.



Plan B: behavioural

1. - Translate the truth table into an algorithm or flowchart.


Schematic_2 flowchart_3
Version (1) Version (2) and (2_2) Version (3)

Fig. 6. Three versions of a plan B description. Versions 1 and 3 are flowcharts, and version  2 is an schematic that adapts the entire truth table artefact to input and output ports.

2. - Save project files here (each behavioural description becomes a complete different project):




3.- Find a similar VHDL circuit with an architecture that corresponds to a truth table or algorithm to copy and adapt. Translate your algorith, flow chart or schematic into VHDL in a single file.



Plan C1: hierarchical in a single file connecting smaller devices of the same kind and other circuits or logic.

1.- Invent an internal architecture composed of several building blocs interconnected together. Analyse Fig. 7, this is the implementation of a MUX_8 using a hierarchical approach composed of a network of components of the same kind and other devices or logic in a single VHDL file (flat).

2.- Use a VHDL description of every block (equations/truth tables or algorithms, etc.) connecting them using signals.

3.- Find a similar VHDL circuit with a similar structural architecture to copy and adapt.

4.- Save project files here: 



Fig. 7. This is an architecture proposed for the MUX_8 organised as a hierarchical design containing components of the same kind (MUX_2, etc., logic gates and wires (signals):

  • Plan C1) place them all in a single VHDL file (not recommended)

  • Plan C2) place the circuit in several files organised hierarchically  (recommended and preferred method in CSD as shown here) . 

And of course there is a multiple-VHDL file method for conceiving the MUX_8:

Plan C2) the same Fig. 7. The implementation of a MUX_8 using a hierarchical approach composed of a network of components of the same kind and other devices or logic in several VHDL files: a top design (MUX_8.vhd) and components (MUX_2.vhd, MUX4_vhd) and signals K, P, Q. This project is fully demonstrated here as a P3 tutorial.

Thus, you can write the VHDL source file MUX_8.vhd using different approaches and be able to compare and discuss advantages and drawbacks of the different VHDL styles.

3. Development

Name the project MUX_8_prj and use one of the EDA tools to implement it selecting a target programmable chip (sPLD, CPLD or FPGA) from our training boards in the laboratory. 

NOTE: Do not write VHDL code without the corresponding schematic / equation / diagram / flow chart / algorithm from the previous planning section. Here in CSD, the VHDL source file is always a direct translation of your sketches represented in pen-and-paper. Submitted VHDL files, project developments and testing will not be marked unless they go accompanied byspecifications and planning discussion.

1.- Write VHDL files. The entity is the same for all the projects since it is related to the symbol in Fig. 2. Note that in this project channel inputs are not considered a vector but individual wires.

NOTE: Use in CSD the Notepath++ enriched text editor, a very convenient free tool for writing VHDL and C files. Another editor is Scriptum from the company HDL Works.



If you follow the Plan A, find structural equations and stuff in this similar tutorial on a Dual_MUX_4. You will require the files MUX_8.tbl, MUX_8.equ to find a simplified equation. This is a file MUX_8,vhd that correponds exactly to the symbol, including the Y_L output as well. 

And, as studied in P1, it is possible to invent two circuits, one of them based on SoP and the other on PoS.


Fig. 8. This RTL schematic of a MUX_8 is from the ON Semiconductor datasheet. You project has to generate something similar when following plan A or plan C1.


If you follow the Plan B, (behavioural), these are up to four versions: (1) MUX_8.vhd; (2) MUX_8.vhd; (2_2) MUX_8.vhd;  (3) MUX_8.vhd, accordingly to the plans infered above.

And if you follow the Plan C1, this is the MUX_8.vhd file, the tranlation of the architecture shown in Fig. 7. This is an example RTL view to be compared with Fig. 8.  

2.- Synthesise the circuit's architecture accordingly to the plans A, B or C1:

Start an EDA tool project for a sPLD/CPLD/FPGA chip MUX_8_prj and obtain the synthesised circuit. It is a project consisting of a single VHDL file (flat design).

Print, analyse and comment the computer generated RTL and technology views or schematics of the circuits.


Discuss the advantages and drawbacks of each development. Compare specifically the RTL and technology views of the three methodologies.


4. Testing

To test the solution whatever it is from plan A, plan B or plan C1, use the same test bench because even if you have different architectures, we use always the same entity definition. This is an example of a simple test bench MUX_8_tb.vhd where the inputs have been stimulated with logic values.

These are the timing diagram preferred colour schemes (already configured) :

- ModelSim Intel Starter Edition: This a colour scheme to be able to print logic analyser results in a white background colour instead of the default black as you see in Fig. 9.

- Xilinx ISE colour scheme (ISim preferences).

- The ActiveHDL Lattice edition colour scheme is already configured by default.

1.- Start an EDA VHDL simulator project to verify the Device-Under-Test (DUT) using a VHDL simulator test bench. The name of the file will be: MUX_8_tb.vhd (if the tool generates a MUX_8.vht, simply rename and copy it at project folder).

2.- Start the simulation process with only a few input vectors (from the timing diagram sketch in the specifications) to see if the whole simulation process works and you are able to watch correctly input and output signals activity. 

3.- Verify applying sufficient test vector that the device works as expected (verify how the information of each channel is selected). Print the timing diagram screen and add comments on the signals to show how the device works.

Some results (from class discussion):

test example

Fig. 9. Example of a timing diagram produced by the simulator with some mandatory comments and discussion on the way the circuit works.

5. Report

Because this is the first VHDL project, special attention has to be paid in annotating all the necessary steps to carry on the design process or flow of a circuit using VHDL synthesis and simulation tools. This design flow will be repeated once and again from this P2 to P8. 

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources. 


6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works. More notes in this lesson about target chips sPLD, CPLD and FPGA. 


Other similar projects on combinational logic circuits

- Encoders, demultiplexers, code converters, dice decoder, wind direction encoder, etc.  Most of the projects of this CSD course are organised and solved in a similar fashion, thus, once you've become aware of it, and have some practice, it'll be something familiar to you. Furthermore, you'll be able to assess yourself and so have a pretty good idea of your grades before a formal reviewing and even without the intervention of your instructor. 

- This file can be used to copy and adapt to translate an encoder truth table to VHDL (plan B).

Other materials of interest

- Q & A.

- Exams, questions, problems and projects

- Multiplexers are basic building blocks that are used everywhere in digital system design. For example, in this serial multiplier you can see how multiplexers are used as one of the many components in the subsystem.