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CSD EXA2: final exam examples and solution ideas

2425Q2

Problem 1.

Example of analytical solution where we have to generate all the signals of interest in several steps, indicating with dots the sampled values of the FF control inputs. When K0 = '1' the circuit generates a periodic sequence of four numbers: 2, 5, 6, 1, 2, ...

Analytical solution

Check your analytical solution with the waveforms captured from the logic analyser instrument. This is an example Proteus simulation solution.

Simulation waveforms

We can design a synchronous canonical FSM that when enabled (K0 = '1') generates the sequence 2, 5, 6, 1, 2, ..., and when disabled (K0 = '0') does nothing, keeping the last value.

Problem 2

One way to solve this circuit is fixing the Counter_mod16 to count always up, as shown in the schematic. The flexibility of this component allows other solutions for the programmable post-scaler frequency divider. It is a good idea to capture the circuit in VHDL or Proteus to verify that the system works as expected. Expanding and truncating counters is explained in L7.3 lecture

EXA2_P2_Post_scaler_divider

Problem 3

This light control is similar and simpler that the Lab 6. Light switches ON and OFF clicking the push-button only one time. Therefore, only four states are required to memorise the PB clicking (Idle, Click_detected_1, Light_ON, Click_detected_2). Four D_FF will be required to encode this FSM when using one-hot code.

Problem 4

The typical FSM solved in C language, similar to many other examples such this Johnson sequencer. The diagram below sketches an example solution.

Sketch P4

Two external interrupts, for instance PB = INT0, CLK = INT1. Six port pins as inputs, for instance PORTD(5..0) and six pins as outputs, for instance PORTC(7..2). The picture also shows one way to shift and rotate 6-bit in a char (uint8_t) variable to be implemented in output_logic() state shift_right. A good idea for experimentation is to complete the project and use the CSD_PICstick board to verify how it works.

Problem 5

This serial transmitter is proposed in P10 as the highlighted project design phase #1.