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Bachelor's Degree in Telecommunications Systems and in Network Engineering |
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Laboratory |
Lab AR: School days (activity restricted) VHDL, FPGA, Flip-flops, FSM, counters, registers, and dedicated processors |
[30 Apr] |
School days (activity restricted). A Chapter III final session to consolidate important ideas and linking concepts on sequential system design.
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Time for revision and discussion on your project PLA6_7.
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Report organisation. Cooperative group work. Group oral presentation
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Your first design phase: the basic FSM in a single file plan C1. Encoding the state enumeration, state diagram, timing diagram, etc.
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Your second design phase: add counters, registers or other operational circuits. Where to find them? How to control these devices?
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Your third design phase. Clock generators and the top design for your PLA as a dedicated processor.
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On plan C2 for counter expansion and truncation. Review the main ideas on the Counter_mod12. How to use the versatile component Counter_mod16?
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On plan Y for large counters and registers. From the small Counter_mod12: how to design a large Counter_mod1572?
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CLK and reset (CD) circuits, flip-flop synchronisation. Why do we have to filter push-buttons circuits (Debouncing_filter)?
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| Web activa des de 09/2001, @ F. J. Robert, Web editat amb Microsoft Expression Web 4. El contingut és un complement als materials d'estudi del curs Circuits i Sistemes Digitals disponibles al campus digital Atenea. Llicència:Reconeixement 4.0 Internacional de Creative Commons |