-------------------------------------------------------------------------------- -- An example of a chip design: Encoder 10-lines to 4-bit binary code (BCD) -- (Type 74LS148) --------------------------------------------------- -- Enc_10_4 structural hiearchical: using components and Plan C2 strategies -- It is the translation of this plan based on Enc_8_3 components: -- https://digsys.upc.edu/csd/P03/enc_10_4C2/Enc_10_4C2.html -- Project P3 - CSD -- http://digsys.upc.edu -------------------------------------------------------------------------------- LIBRARY ieee; USE IEEE.STD_LOGIC_1164.all; entity Enc_10_4 is port ( D_L : in STD_LOGIC_VECTOR(9 downto 0); Ei_L : in STD_LOGIC; Y : out STD_LOGIC_VECTOR(3 downto 0); Eo_L : out STD_LOGIC; GS_L : out STD_LOGIC ); end Enc_10_4; ARCHITECTURE hierarchical_structure OF Enc_10_4 IS -- The elemental components to be used: COMPONENT Enc_8_3 IS PORT ( D_L : in STD_LOGIC_VECTOR(7 downto 0); Ei_L : in STD_LOGIC; Y : out STD_LOGIC_VECTOR(2 downto 0); Eo_L : out STD_LOGIC; GS_L : out STD_LOGIC ); END COMPONENT; -- Signals SIGNAL Y22, Y12, Y02 : STD_LOGIC; -- internal wires SIGNAL Y21, Y11, Y01 : STD_LOGIC; SIGNAL GS_L1, GS_L2 : STD_LOGIC; SIGNAL Eo_L2, Eo_L1 : STD_LOGIC; BEGIN Chip1 : Enc_8_3 PORT MAP ( -- from component name => to signal or port name Ei_L => Eo_L2, D_L => D_L(7 downto 0), Y(2) => Y21, Y(1) => Y11, Y(0) => Y01, GS_L => GS_L1, Eo_L => Eo_L1 ); Chip2 : Enc_8_3 PORT MAP ( -- from component name => to signal or port name Ei_L => Ei_L, D_L(7) => '1', D_L(6) => '1', D_L(5) => '1', D_L(4) => '1', D_L(3) => '1', D_L(2) => '1', D_L(1 downto 0) => D_L(9 downto 8), Y(2) => Y22, Y(1) => Y12, Y(0) => Y02, GS_L => GS_L2, Eo_L => Eo_L2 ); -- Other circuits and equations: Y(3) <= not(GS_L2); Y(2) <= Y22 or Y21; Y(1) <= Y12 or Y11; Y(0) <= Y02 or Y01; GS_L <= GS_L1 and GS_L2; Eo_L <= Eo_L1; END hierarchical_structure;