-------------------------------------------------------------------------------- -- A standard circuit Enc_8_3 : Encoder from 8 keys to 3-bit binary (or BCD) -- Behavioural approach (Plan B) -- This is the translation and adaptation to 8-lines of the schematic -- representing the truth table Fig. 6 in this page: -- https://digsys.upc.edu/csd/P02/enc_10_4B/Enc_10_4B.html --------------------------------------------------- -- Project P2 - CSD : standard logic circuits in VHDL -- http://digsys.upc.edu -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- To be able to translate "std_match" entity Enc_8_3 is port ( D_L : in STD_LOGIC_VECTOR(7 downto 0); Ei_L : in STD_LOGIC; Y : out STD_LOGIC_VECTOR(2 downto 0); Eo_L : out STD_LOGIC; GS_L : out STD_LOGIC ); end Enc_8_3; -- The connections to the truth table artefact -- Circuit truth table is described in Fig. 2 at: -- https://digsys.upc.edu/csd/P02/enc_10_4B/Enc_10_4B.html -- (simply with the adaptation to 8-inputs and only 3-bit outputs) architecture Truth_table of Enc_8_3 is SIGNAL Xin : STD_LOGIC_VECTOR (8 downto 0); SIGNAL Yout : STD_LOGIC_VECTOR (4 downto 0); begin -- Xin (8, 7, 6, 5, 4, 3, 2, 1, 0) --> Ei_L D_L(7) ... D_L(0) -- Yout(4, 3, 2, 1, 0) --> GS_L Y(2) Y(1) Y(0) Eo_L -- This is the very convenient statement to be used when "don't care" inputs Yout <= "10000" when std_match(Xin,"011111111") else -- no key pressed "00001" when std_match(Xin,"011111110") else -- Key 0 clicked "00011" when std_match(Xin,"01111110-") else -- Key 1 clicked "00101" when std_match(Xin,"0111110--") else -- Key 2 clicked "00111" when std_match(Xin,"011110---") else -- Key 3 clicked "01001" when std_match(Xin,"01110----") else -- Key 4 clicked "01011" when std_match(Xin,"0110-----") else -- Key 5 clicked "01101" when std_match(Xin,"010------") else -- Key 6 clicked "01111" when std_match(Xin,"00-------") else -- Key 7 clicked "10001"; -- disabled -- In this way we write 512 input combinations -- The simple buffers to attach the inputs and outputs to the truth table -- Input connection Xin(8) <= Ei_L; Xin(7 downto 0) <= D_L; -- This is a block of 8 buffers -- Output connection GS_L <= Yout(4); Y <= Yout(3 downto 1); -- this is like a block of 3 buffers Eo_L <= Yout(0); end Truth_table;