UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Digital Circuits and Systems (CSD) 

20-21 Q2

 


Intended learning outcomes, organisation, projects and exams

Our main learning objective is that upon completion of the course, you will be able to:

Systematically specify, plan, develop, simulate, report, prototype and verify simple digital circuits and systems, using state-of-the-art digital programmable devices and microcontrollers, CAD/EDA software tools and laboratory equipment, by means of cross-curricular competences and PBL methodology.

- This course will be taught in a synchronous online mode using Google meet.  

- The way to attend CSD is simple: let's study and design a project every week by means of this planning schedule and PBL techniques. NOTE: Even if you find PBL (and this digsys book) confusing or somewhat disorganised we assure you that there is nothing like learning by doing practical examples and at the same time studying the required theory.

- The course workload is 150 hours or 6 ECTS. This is a short presentation rec. of our course organisation and syllabus.

- Laboratory assessment P_Ch1, P_Ch2 and P_Ch3 will be based on lab work in progress and your submitted handwritten projects, sketches, solutions and oral presentations at Atenea platform. Documenting reports using word processors is optional in final P_Ch3.

- This is an archive of CSD exams with solutions, problems and questions. These are video recordings to clarify specific topics, concepts and proceeding when using EDA tools and designing circuits. This is the syllabus of CSD as a book table of content; just a way to show you that main topics in books on fundamentals of digital circuits and systems are covered in our course.

- You are encouraged to participate actively in class or by email,  post questions and answers in our Atenea blogs and help as much as possible your mates working in cooperation as in a real-world company.

 

- Software resources:

Chapter 1 Chapter 2 Chapter 3
PROTEUS VSM, Notepad++
VHDL C language
minilog.exe. EDA tools for CPLD/FPGA synthesis and simulation: Lattice Semi ispLEVER Classic - Diamond / ActiveHDL,  Intel Quartus Prime / ModelSim Starter  or Xilinx ISE-Vivado/ISim EDA tools for microcontrollers: Microchip (PIC18F/16F/Atmega) MPLABX / XC8

 

Proteus NEWS (April 2021): All CSD software can be download to your portable or home computer. Ask us for Proteus Cloud Licence and use version 8.12. 

- This is the web page from where you can print documents using EETAC printer - scanner machines.

- Optionally you can show and archive your projects and reflections by means of constructing your ePortfolio. This device allows discussion on what you have learnt in this 6 ECTS university course. These materials will be useful for you in other subjects in electronics or even in your final bachelor thesis.