﻿ Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC - UPC  Bachelor's Degree in Telecommunications Systems and in Network Engineering ## P5: analysis of circuits based on flip-flops and latches

Resources in lectures and labs L5.1, Lab5 L5.2 on memories, Use these tutorials to inspect 1-bit memory cell specifications:  D_FF, JK_FF (and also RS_FF), T_FF.

Example analysis: asynchronous circuit based on T_FF

1. Specifications

Analyse circuits based on flip-flops and latches. This classic chip DM74LS93/92/90 is an example on how flip-flops and logic gates are used to build digital circuits with memory capacity.

A. Method 1: Analyse the circuit in Fig 1 drawing a timing diagram sketch to see how each flip-flop evolves in time. Determine what kind of output codes are generated each CLK cycle. What is the function of this circuit?

B. Method 2: Capture the circuit in Proteus and run simulations to check whether your paper analysis is correct. Use the logic analyser instrument to represent both inputs and outputs in function of time.

C. Method 3: Capture the circuit in VHDL as a plan C2 structure, synthesise it and run a simulation testbench to represent all inputs and outputs in time in a waveform logic diagram.

D. Demonstrate the drawbacks associated with asynchronous designs running a gate-level simulation. Pay attention in output transitions and explain what happens from one output code to the next. Fig. 1. Symbol and schematic of the asynchronous circuit to be analysed. CLK is a rectangular wave of TCLK period. Clear direct (CD) is a single pulse any time the user like to initialise the circuit. E. Enhance the circuit in Fig. 1 as shown in Fig. 2, adding a decoder Dec_4_16 to convert the 4-bit output codes to one-hot for better observing how poorly is performing in transitions from one code to the next. Fig. 2. Symbol of the modified circuit with 16-bit one-hot vector output Q(15..0).

As usual in CSD, before attempting this analysis project, we need to review materials, theory and other similar examples of asynchronous and synchronous circuits.

Other similar analysis problems: Solve similar asynchronous circuits in problems 5.4, 5.8 and 5.9 in the collection. This is problem 5.9 solution. This is a video  on problem 5.4 solution, the last part of which shows how to deduce the timing diagram in paper. Solve synchronous circuits in problems 5.3 and 5.5. Highlight differences between synchronous and asynchronous circuits.

2. Planning (up to three strategies to solve the problem)

A. General procedure for analysing circuits based on flip-flops. Timing diagram and the number and value of states must be deduced. States in this circuit are associated to the generated binary codes.

- Identify the many CLK signals in the circuit. Is it asynchronous or synchronous? Go step by step advancing in time (which means advancing by TCLK periods (circuit's time resolution).

- Be sure to identify which T input values are sampled at the CLK's rising edge. To do it, consider the small tCO (in the range of ns) associated to each output transition.

- Once the timing diagram is completed, determine the number of states and what the binary output for each state is. Fig. 3. Example of timing diagram and analysis discussion. The complication of this circuit is related to the several CLK signals CLK, CLK1, CLK2, CLK3 delayed each other TCO, and thus false output codes are generated at signal transitions.

B. Draw your circuit L:\CSD\P5\Proteus\Circuit_async.pdsprj and simulate in Proteus. Verify your solution using the logic analyser instrument. This a Proteus circuit to play with flop-flops as if we were in the laboratory building such circuits for real using classic 4000 CMOS series. When picking parts from the library to mount your circuit, do this initialization --> Tool --> Global Annotator --> Total. Adapt it to your circuit like Circuit_async.pdsprj.  Fig. 4. Example of circuit captured in Proteus with logic analyser results.

C/D.The internal architecture of the circuit proposed in Fig. 1 has to be fully annotated as in Fig.5 before developing the VHDL project. The flip-flop description in VHDL is available in its tutorial T_FF. This is a plan C2 project of two files:

L:/CSD/P5/VHDL/(files) Fig. 5. Circuit fully annotated and ready for translation to VHDL.

E. It is even easier to visualise the problems of this circuit converting it into a 16-bit one-hot circuit by means of a binary decoder Dec_4_16 component to translate outputs from 4-bit radix-2 to 16-bit one-hot.

L:/CSD/P5/Circuit_async_onehot/(files) Fig. 6. Schematic of the asynchronous circuit with one-hot outputs designed to observe the poor performance of asynchronous circuits based on CLK rippling or using CLK as another logic signal to control flip-flops.

3. Development or carrying out the plan

C/D. Write down the VHDL file corresponding the Circuit_async.vhd from the schematic above in Fig. 3. Use T_FF component from its tutorial. Inspect and analyse the RTL schematic generated by the synthesiser EDA tool. Fig. 7. RTL produced by the synthesiser. Fig. 8. Technology schematic to be tested using gate-level simulations. In red is represented the CLK path from one T_FF to the next. Note how four D_FF registers are used, one per T_FF.

E. This is VHDL description for the decoder Dec_4_16.vhd component translating this plan B. Thus, the project resulting from the translation of Fig. 6 schematic Circuit_async_onehot.vhd will generate one-hot outputs. Fig. 9. RTL produced by the synthesiser of the project with one-hot outputs.

4. Testing (functional)

Fig. 10 shows the generalised VHDL testbench schematic that we have in mind to run simulations for our sequential systems under test. Remark the significant change replacing Min_Pulse constant by CLK_Period to define from now on time resolution. Fig. 10. General testbench fixture for sequential systems, including at least two stimulus processes: one for the CLK and another for the remaining input ports.

Fig. 11 represents the inputs required in this experiment. A periodic CLK waveform of rectangular shape, for instance with a duty cycle = 25% and a clear direct CD pulse that can be repeated when necessary to initialise again the circuit. Make all the timing relative to the constant CLK_Period, that is the equivalent in Chapter 2 to the Chapter 1 contant Min_Pulse. Fig. 11. CLK and CD activity to be described in the testbench processes. From this activity the simulator will calculate outputs. Normal operation of the circuit can be inspected for example setting CLK_Period = 4 us. And detailed time measurements on signal transitions can be performed setting CLK_Period = 40 ns when testing the real technology view synthesised circuit for a given target chip (FPGA or CPLD).

C/D. Start the testbench template and add CLK and inputs activity translating input signals in the timing diagram. Thus, to test sequential systems at least two stimulus processes will be required: the CLK process and another process for all the other inputs. This is an example testbench file Circuit_async_tb.vhd.

Functional simulation. Run the EDA VHDL tool and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms. Fig. 12. Waveforms from functional simulation. This circuit looks like that is acting as a 4-bit binary counter in radix-2.

5. Testing (gate-level)

C/D. Gate-level simulation. Run the EDA VHDL tool using the same test bench and demonstrate CLK to output propagation delays (tCO) and calculate the maximum frequency of operation. Fig.13. Results from a gate-level simulation zooming all the test time to see that it works as expected. Fig. 14. Results from a gate-level simulation focusing a single transition in a ns time window.

E. Similar waveforms in the logic analyser can be observed running Counter_onehot_16bit_async using a similar testbench Circuit_async_onehot_tb.vhd Fig. 15. Results from a gate-level simulation focusing a single transition in the Circuit_async_onehot.

6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.

7. Report

It is required a handwritten original project report containing sections 1 - 2 - 3 - 4 - 5, scanned figures with annotations, file listings, diagrams, sketches or any other resources. Theory stuff to comprehend how the circuit works may be included in section 1 on specifications.

Other similar projects on sequential circuits

- Thus, in the end, if these asynchronous circuits behave so poorly, which is the right way to design sequential circuits? The answer in next P6: Synchronous canonical sequential circuits based on FSM architecture.