UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

P9

P10: FSM in C language (software FSM), external interrupts

P11
Resources in lectures and labs: L10.1, Lab10, L10.2 Project objectives

Highlighted project: 4-bit serial transmitter (design phase #1)

1. Specifications

Let us design a simplified 2-wire (Serial_out - GND) asynchronous data transmitter based on a μC for sending a nibble (4-bits) of data to another computer or device. The symbol is represented in Fig. 1. Asynchronous transmissions based on Shift_Reg_4bits devices were studied in the USART tutorial (rec. part 1).

The target chip is PIC18F4520. We will program the application in C language using our FSM style. The format for the serial output once the start-transmission (ST) rising edge is detected by means of an interrupt is: Start bit ('0'), Data_in (0), Data_in (1), Data_in (2), Data_in (3); Stop bit ('1') and while transmitting the stop bit, the end-of-transmission EoT pulse is generated to indicate that the transmitter has ended the process. The output Serial_out is held high when idle.   

Symbol

Fig 1. Symbol for the 4-bit serial transmitter.

Fig. 2 shows an example of timing diagram to start transmitting data when the ST pulse is detected.

Timing

Fig 2. Example of a section of a timing diagram where it can be seen how the data is read and right shifted in a single wire.

Serial transmission (TX) and reception (RX) is used in every electronic equipment. For instance, Fig. 3 shows two examples:(a) the PC computer COM serial port and its options; (b) the communication between ECU (electronic control units) in modern autonomous vehicles.

a) PORT COM

b) autonomous vehicle

Fig 3. a) Example of PC COM port. b) Autonomous vehicles generate huge amounts of data to be transmitted from and to high-speed digital subsystems. Reference: Keysight white paper: "High-Speed Digital Design Success Demands A Modern Workflow" (pdf).

 

Other design tutorials and assignments.

The idea that we have in mind in this Chapter 3 on designing software FSM is well explained in this white paper from ARM.

 

2. Planning

A) Planning hardware

The electronic circuit sketch is shown in Fig. 4. Some μC port pins are selected to be inputs and outputs, external interrupt INT1 is used to detect ST active edge event (falling or rising signal transition) to start sequencing the transmission. External interrupt INT0 will detect an active edge from the external CLK to be able to serialise one bit per period. The key concept detecting signal edges using interrupts. CLK interrupt can be both, enabled all time or instead, only after start transmission edge is detected.

Example hardware schematic Fig. 4. Hardware used in this application. The 2-wire serial output cable can be simulated using a resistor R0 = 10 kW. 

PIC18F4520 has three port pins  (RB0, RB1 and RB2) able to generate external interrupts (INT0, INT1 and INT2) when detecting signal edges.

 

B) Planning software

The general idea is represented in Fig. 5 (rec. part 2). The concepts of CC1 and CC2 combinational circuits inherited from Chapter 2 have the same meaning, we will implement this logic using software routines.

structure

Fig. 5. Software organisation used in this application. Because current_state is saved in a memory position and updated every main loop cycle, there is no need of next_state variable as it was the case in Chapter 2.

And even a clearer flowchart reorientation of the software organisation in Fig.6 below.

structure
  Fig. 6.  General interrupt-driven FSM-style program organisation (Visio).

Therefore, it is possible to think in terms of a kind of hardware/software diagram as shown in Fig. 6. The idea of implementing a "FSM in software": state and output logic connected to RAM variables and some functions related to hardware (drivers) to read and write external pins. 

Hardware-software diagram
Fig. 7. This diagram connects in a convenient way the hardware section and the software functions for better understanding the idea of programming FSM. 

Draw the state diagram, so that the sequence presented in Fig. 2 can be generated after having detected an ST edge.

State diagram 
  Fig. 8. Proposed state diagram. Be aware that all the signals represented are RAM memory variables, for instance, CLK is var_CLK_flag. When the ST button active rising edge is detected, the FSM needs six CLK periods to complete the transmission and to go back to idle state to wait for the next ST pulse. 

In Fig. 9 there is the representation of the RAM memory required in this project.

RAM Fig. 9.  We will use six bytes of RAM to store the variables.

At this introductory level, memory positions are not optimised in any way. Our main goal is clarity, and thus, we like to save each signal in a different memory position zeroing all the unused bits.

Another convention to make it simple is to code FSM states in the variable current_state  using ASCII capital letters to facilitate interactive debugging using watch windows. 

Draw the main ideas of init_system(). Configure input and output pins. Consider as well interrupts configuration.

Fig. 10. Example of TRIS configuration

Draw the flowchart of read_inputs(). Basic function to poll input voltages as in P9. 

Draw the flowchart of write_outputs(). Basic function to write pin voltages as in P9. 

Infer how to organise the interrupt service routine ISR() to handle edge detections.

And now, it is necessary to discuss how to transfer all the state transitions into a truth table.

Draw state_logic() truth table

Truth table for state_logic
  Fig. 11. Truth table for state_logic() function.

Translate it into a behavioural flowchart.

Flowchart CC1
  Fig. 12. Translating state_logic() truth table into a behavioural flowchart so that C statements can be easily imagined. 

 

Finally, what is left to finish this project planning is the same idea but for the outputs, how to translate all the outputs in parenthesis into a truth able and the equivalent flowchart?

 Draw output_logic() truth table.

Output logic truth table
  Fig. 13. Truth table for output_logic() function.

Translate it into a behavioural flowchart.

CC2 flow chart
  Fig. 14. Translating output_logic() truth table into a behavioural flowchart so that C statements can be easily imagined. A Moore FSM makes it simple than a Mealy FSM, all the outputs are perfectly defined for each state.

 

Organise a MPLABX - XC8 IDE project targeting a PIC18F4520 at location:

C:\CSD\P10\Serial_transmitter\(files)

 

3. Development - 4. Testing interactively

A) Developing hardware

Electronic circuit and C source code. Running simulations and debugging ( rec. part 3).

This is a file Serial_transmitter.pdsprj containing the circuit represented in Fig. 15. Be aware that ST and CLK inputs must be connected to external interrupts like RB1/INT1 and RB0/INT0.

Circuit
Fig. 15. The proposed circuit running the final executable "*.cof" to be able to debug errors and step by step mode.

 

B) Developing software

Planning ideas in previous sections are translated to Serial_transmitter.c source file.

Run the microcontroller's IDE to develop and compile the C code to obtain executable files.

 

C) Step-by-step testing

These are the project files where the Serial_transmitter project runs in Proteus environment. Instrumentation can be used to display transmitted waveforms. You may like to replace the ST button by a pulse generator (for instance 0V-5V, T = 1 s, pulse duration = 20 ms).

Remember that development and testing must be carried out step by step, one feature at a time.

waves and circuit
Waves Fig. 16. Waveforms captured in Proteus showing the transmission of the four bytes once the start bit is low. 

NOTE: Do not print these pictures with black background. Configure and change colours to save ink when printing pictures for your reports.

 

- Check that the machine is always under control running through the enumerated states (watch window --> current_state).

- Check  the duration of a transmitted bit using breakpoints.

- Check that var_ST_flag has the right values when start transmission button is pressed.

- Calculate how fast is the main loop.

 

5. Report

Project report: sheets of paper, scanned figures, file listings, notes or any other resources. Follow this rubric for writing reports.

 

6. Prototyping

Example 1: Board Picdem2+. Target microcontroller: PIC18F4520.  Tools: MPLAB X + XC8 + Proteus

PicDem2Plus

Fig. 14. PICDEM2+ board to be used with a PIC18F4520 chip. Expansion connectors or prototyping area can be used to connect switches and LED.

 

Example 2: Board Explorer 8. Target microcontroller: PIC18F4520.  Tools: MPLAB X + XC8 + Proteus

Explorer 8

Fig. 15. Explorer 8 board to be used PIC18F4520 chip. The same code as in the previous example.

 

Example 3 optional, beyond the CSD learning objectives. Board Explorer 8. Target microcontroller: PIC18F46K22.  Tools: MPLAB X + XC8  + MCC + Proteus. Project: Interrupt

To take full advantage of this board the programming environment requires MCC (MPLAB Code Configurator) application embedded in MPLAB X. The chip must also be upgraded for instance to PIC18F46K22, which is also available in Proteus.

This is an introductory project Interrupt.pdsprj to guide you on the use of MCC to specify hardware and peripherals. It is the same project presented in P9 where the push-button S1 generates INT0 interrupts to update Var_SW_S1. The application program Interrupt.zip is organised in multiple c files. Unzip and copy the full directory at location:

C:\CSD\P10\Interrupt\(files)

Interrupt seed project to learn on interrupts and EXPLORER 8

Fig. 16. This application can be used as a seed project to copy and adapt, no need to start from scratch. The full tutorial application that exemplifies several features of the hardware in Explorer 8 is available from Microchip product page.