UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

SP3_1

Q&A

SP3_2: Prog_Timer design phase #1. FSM and external interrupts

SP3_3

Lab10


NOTE: This subproject must be solved only after having completed successfully lab session Lab10 because you will copy and adapt materials from it.

1. Specifications

Prog_Timer design phase #1: Adapting FSM to μC using external interrupts. The aim of this preparatory laboratory assignment is to analyse the given circuit for the programmable timer and complete hardware and software.

Circuit

Fig. 1. Circuit.

 

2. Planning

Project organisation is similar to other Chapter projects in P10 and Lab10. Study all the project sections given in this page and draw the truth table and its equivalent flowchart for state_logic().

Hardware circuit

Fig. 2. Schemetic of the harware circuit that has to be developed in Proteus.


Paper work on diagrams, sketches, flowcharts and materials for studying the project in detail and completing it.

hard-soft diagram

Fig. 3. is an example of hardware-software diagram.

 

 

Software flowchart

Fig. 4. General software organisation.

 

RAM

Fig. 5. RAM variables.

 

State diagram

Fig. 6. State diagram.

 

Initialisation

Fig. 7. Initialising the system.

 

Reading inputs

Fig. 8. Reading inputs.

 

Writing outptus

Fig. 9. Writing outputs.

 

ISR()

Fig. 10. ISR()

 

Counter datapath

Fig. 11.Counter datapath.

 

Truth table
flowchart

Fig. 12.Truth table and flowchart for the function output_logic().


Thus, once analysed all these materials, you are ready for discussing the state_logic() truth table and its equivalent flowchart.

hardware

Fig. 13.Truth table and flowchart for the function state_logic() yet to be planned.

Project location:

C:\CSD\P_Ch3\SP3_2\(files)

 

3. Developing and 4. testing

This Prog_Timer.pdsprj is the capture of the hardware schematic in Fig. 2 above.

Start a new MPLABX project Prog_Timer_prj using this seed Prog_Timer.c source file. Compile and verify in Proteus that your application runs with no errors. Tranlate into C the state_logic() function planned above in Fig. 13. Run, debug and make measurements as represented in Fig. 14 to show how your circuit works for different PC values.  

running

Fig. 14. Example of oscilloscope measurements and watch window for debugging purposes.

 

Additional measurements and questions once the circuit is in operation:

 

5. Report

Follow this rubric for writing reports.