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P2 objectives |
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After studying the content of these projects, you will be able to:
Explain the specifications and characteristics of the standard combinational logic blocks: multiplexers (or data selectors), de-multiplexers (or data distributors), decoders, encoders, hexadecimal to seven-segment LED displays adapters, code converters, etc. Specifications include concepts like: symbol, truth table and functionality, internal design, expandability, and commercial chips of similar characteristics.
Explain the functionality of the enable input that is available in most of these standard circuits.
Explain the concepts of flat and hierarchical designs and implement simple projects in VHDL involving a single file (flat) using structural (plan A) or behavioural (plan B) approaches.
Explain how to chain or expand such devices to implement a larger one, for instance, how to connect several MUX_4 to obtain a MUX_16.
Implement standard circuits targeted at a given PLD (CPLD or FPGA) using VHDL and synthesis and simulation EDA tools. Explain the VHDL design flow.
Find datasheets of classic logic circuits from different technologies.
Explain how to interface switches to encoders.
Explain how to interface LEDs and seven-segment display to decoder outputs.