upc eetac_1 Bachelor's Degree in Telecommunications Systems and in Network Engineering

Project P1 tutorial: Installing and using Proteus-ISIS

P1


Computer simulation (virtual electronics laboratory) based on SPICE algorithms 

1. Specifications

Capture a logic circuit in a Proteus project, and run simulations with the aim of obtaining its truth table. These are a pair of circuits for practising: Circuit A , Circuit B .

Proteus is a virtual laboratory, a SPICE based electrical simulator. Its advantage for our course is that you can simulate both analogue and digital circuits based on microcontrollers (Chapter 3 from P9).

1. Installation

The software is installed and available at EETAC laboratories and computers.

Proteus

Fig. 1. Software logo.

 

2A. A flat design example

This is a simple flat (all the design at the same sheet of paper) circuit Comb_circuit.pdsprj. It can be adapted for other similar projects.

circuit

Fig. 2. A simple circuit that you can use as a template to adapt it to your design. The latest tutorials form the company.

This is another circuit Circuit_W.pdsprj as an example that were copied and adapted from the circuit above.

Interfacing real components. The circuit in Fig. 3 is another version  Circuit_W_real.pdsprj where you can add to the digital electronic circuit Chip1 some buttons, switches, LEDs and even relays and motors. Play with the circuit and pay attention to the real voltages and corrents that represent '0' and '1' signals.

real circuit icon

Fig. 3. Another digital circuit including real components (click the picture to zoom) to interface buttons and power loads.

In Fig. 4, there is the detail of a power driver based on a simple bipolar junction transistor (BJT) and an electomechanical relay.

Motor driver

Fig. 4.

 Logic gates manage uW of power, but conveniently amplified, can easily drive electric loads. In this example a kW motor is switch ON and OFF.

 

2B. A hierarchical design 

The adder_subtractor_8bit.pdsprj occupies multiple structured hierarchical sheets of paper. Such top-down circuit organisation that will allow us to build large circuits will be studied from P3 using VHDL instead of schematics. 

structural

Fig. 5. The subcircuit block allows packing circuits in boxes or "entities"that can be used many times in the same schematic.

 

This example can be takes as a hierarchical template circuit to copy and adapt.

 

Other similar tutorial exercises

- Here you are another hierarchical schematic of a hexadecimal to 7-segment decoder which is solved using logic gates.

- This is the same hexadecimal to 7-segment decoder but solved using a simple programmable logic device 22V10. Thus, the circuit pdsprj and sPLD configuration file jed have to be placed in the same folder. Logically, the jed file is obtained in the end of the design process using VHDL language and an EDA tool such as Lattice ispLEVER Classic. 

- This is the same project Circuit_W solved with another very powerful and full-featured SPICE simulator: MultiSim from National Instruments. As a UPC student you can download the software bundle Multisim (simulator) and Ultiboard (PCB design) for education and obtain a licence. These are instructions if you are interested in such EDA tools for other EETAC subjects.

Circuit_W
 

Fig. 6. Multisim circuit example.

 

Other materials of interest

- To show you the software possibilities, this is a simple Example_Arduino.pdsprj of the simulation of circuit based on an Arduino board. It generates a programmable PWM waveform. 

Circuit with Arduino

Fig. 5. Example of a circuit based on Arduino running in Proteus.